The 12-million transistor chip integrates two banks of 32-Mbit DRAM, 1.2 Mbits of data buffer SRAM, and Mitsubishi's 32-bit D90V media processor core. It is capable of encoding 422P@ML video, and can be configured into a six-chip HDTV encoding module that effectively reduces the A3-sized footprint of present systems to that of a PC Card, the company said. The chip can also process two channels of Dolby digital, two channels of MPEG-1 Layer 2 and two channels of PCM video in both NTSC and PAL formats.

The decoder consumes about 0.7 watts, or nearly half as much as the logic, SRAM, I/O and DRAM it replaces, according to Mitsubishi. The triple-well, four-level copper wire chip will be built on a 0.13-micron process. Samples have been promised for 2002, but the timing of the encoder's production is not yet clear, a company spokesman said.

Mitsubishi is currently ramping its 0.15-micron process and is placing embedded memory into a series of low-power products aimed at portable applications. The 300-mm fabrication facility expected to run the company's 0.13-micron process in Kochi, Japan will not be ready for production until sometime around mid-2003, the spokesman said. Groundbreaking for that fab will start later this year, with the basic building scheduled for completion in 2002.

Matsushita Electric Industrial Co. contributed to the encoder's development. In March, Mitsubishi and Matsushita prototyped a low-power, high-density embedded DRAM technology that could be scaled to a 64-Mbit density on a 10-mm square chip with 10 million gates of logic. The single-chip MPEG-2 encoder is aimed at handheld devices such as MD camcorders, DVD camcorders and HDD recorders, the companies said.