Vitesse sees InP as a preferred substrate for high-speed optical interfaces, and perhaps for some RF applications as well, said Alan Huelsman, director of the company's indium phosphide project. "We see this as very similar to what we did in GaAs MESFETs 15 years ago," he said. "We took a well-characterized process out of academia and made it manufacturable."

Vitesse first announced its intent to use InP for most 40-Gbit parts a year ago, though the company also is working in silicon germanium.

InP is often mentioned as an ideal substrate for optoelectronic integration because it is believed to be easy to add optical components to an InP die with circuits such as a transimpedance amp. While electronic/photonic integration was critical for Vitesse, Huelsman said that breakdown voltage was of equal or greater importance. Since lasers cannot be directly modulated at 40 Gbits, they require an electro-absorption modulator or lithium niobate modulator, he said. Such modulators require very high breakdown voltages, virtually necessitating an advanced process like InP, he said.

Vitesse now manufactures most of its gallium arsenide devices at its 6-inch wafer fab in Colorado Springs, Colo., which allows it to use the 4-inch line in Camarillo as a test bed for indium phosphide. As the process matures and 6-inch InP epitaxial wafers become available, Vitesse will shift some InP manufacturing to Colorado Springs, though that is unlikely to happen before 2004 at earliest, Huelsman said.

Vitesse sees two applications for InP beyond native 40-Gbit parts. Because of its ability to support optoelectronic integration, the process will be used for certain high-integration 10-Gbit/s (OC-192) designs. Also, Vitesse will work with RF component manufacturers to provide foundry service for certain power amps and other components used in 3G cellular applications, though no agreements are in hand today.

To ease line card design at 40 Gbits, Vitesse has designed its own brass package for InP parts, featuring GPPO connectors with oblique angled interfaces that make it easy to link rigid coaxial connectors to the line card, the company said. Power signals and 2.5-Gbit signals can then exit and enter from the top and bottom of the package. In the brass test package, Vitesse mounted a chip face down on the bottom of the package, surrounded by a ceramic pc-board. Vitesse hopes to migrate the design to a standard leaded chip carrier over time.

Vitesse said that everything in its InP process is aimed at reliability and manufacturability. The HBT process uses a transistor built in epitaxial layers, with components mesa-etched from the substrate, using no planar implants. Aluminum metallization is used in all designs, with no air bridges or lift-off metals. The epitaxial layer contains no aluminum, however, since there are questions on the reliability of epi layers that contain aluminum. Vitesse standardized on a carbon-doped layer stack, after rejecting beryllium, magnesium, and zinc dopants as more difficult to use.

Huelsman said OEMs have not been reticent to consider InP devices, and many are skeptical of claims that SiGe or BiCMOS processes can handle anything but rudimentary functions at 40 Gbits/s. While other manufacturers claim to be looking at InP as an alternative process for OC-768 products, Vitesse anticipates enjoying several quarters of being the only semiconductor company shipping products based on InP.