KYOTO, Japan — Samsung Electronics Co. has built a 4-Gbit synchronous double-data-rate DRAM prototype in 0.11-micron technology, according to a presentation at the VLSI Technology Symposium.
While Samsung will be able to produce samples as early as 2004, the company does not yet see applications that will require the 4-Gbit density, said principal engineer Hong-Sik Jeong. Until those applications surface, Samsung intends to apply the design and process lessons learned in the 4-Gbit project to other DRAM densities, Jeong said.
Samsung engineers developed working 80-nanometer transistors for the memory cell array of the 4-Gbit prototype, plus triple-level chemical vapor deposition (CVD) technology.
Single-bit and twin-bit failures are a nagging challenge in the 4-Gbit DRAM generation, Samsung said. One solution is to use a dry clean process involving nitrogen trifluoride to clean surface oxide and residual carbon left from the dry etch process steps.
Samsung also developed a new capacitor for the design, adding a concave structure to the capacitor cylinders to prevent storage node twin-bit failures.
Samsung then used a triple-level CVD process to relax the pitch in the core, reducing block failure and boosting performance by minimizing interconnect delay. Use of an extra metal layer also made it possible to increase power input, said Seung Hoon Han, a senior engineer at Samsung's system LSI division.
The 4-Gbit prototype measures 645 mm square, which is too large for practical production. However, Samsung will apply smaller transistors, contact technology, and a new capacitor design up and down the company's memory density range, said Jeong. The processes developed at the 4-Gbit level can be applied to 8-Gbit DRAMs that will be built with 70- to 80-nm design rules, Jeong said. At the 8-Gbit density, Jeong said Samsung needs to do more work on metal-insulator-metal (MIM) capacitors that use tantalum oxide with ruthenium.
Making capacitors at such small dimensions "becomes critical at the 8-Gbit density," he said. "We can do it if we develop the MIM capacitors, and ruthenium is one of the key candidates" for the MIM structure.
Meanwhile, the technologies developed for the 4-Gbit device will also be applied to help shrink the 256-Mbit and 512-Mbit DDR DRAMs, Jeong said.
