"We want to achieve a manufacturable process that will work with any one of the quantum-computing architectures being proposed today," said project leader Paul R. Berger, an associate professor of electrical engineering at Ohio State University. The effort will be undertaken with the assistance of the University of Illinois at Urbana-Champaign, the University of Notre Dame, the University of California at Riverside, and the Naval and Air Force Research Laboratories.

"A lot of people have successfully demonstrated that quantum-dot nanoswitches of various architectures can work — such as my work on resonant tunneling diodes, or the work of other team members on single-electron transistors and quantum cellular automata — but there is no readily available chip-manufacturing process yet," said Berger.

Today, researchers experimenting with quantum computer chips must craft their own process technology, often trading off manufacturability, good yields, room-temperature operation, reliability and repeatability for small size. That's because most quantum devices won't work at all unless they are very very small.

Quantum dots store information in domains that are at least 10 times smaller than those typically proposed for future silicon chip technologies — only a few square nanometers, containing 50 to 10,000 atoms per stored quantum bit (qubit). The devices work by instantaneously passing individual electrons across an insulator without taking any time to physically pass through it — a phenomena called "tunneling."

Tunneling in quantum dots results from the "probability wave" nature of electrons. Since there is a finite probability that an electron can turn up on the other side of an insulating barrier, quantum mechanics predicts that some electrons will turn up on either side, depending on the prevailing "environmental" conditions.

In addition to tunneling, each nanosize domain can store both a 1 and 0 simultaneously by virtue of what is called "superposition" within their qubits. Superpositions keep the logical state of a qubit nebulous until called upon to "report" in a result. Hence, qubits simultaneously represent both 1 and 0 and can consequently perform calculations that superimpose intermediate steps atop one another in parallel, only later picking out the desired end result from multiple possible calculations.

For instance, superposition enables an 8-qubit adder to simultaneously perform all possible 8-bit additions to all possible 8-bit values. After the addition, an individual result can be picked out from among the 512 possible results that are superimposed atop each other in a single machine cycle by the qubit adder.

Dismal yields

So far, however, most researchers have been concerned with getting their particular method of making quantum dots to actually work, regardless of how difficult the manufacturing effort. According to Berger, all quantum-dot projects so far have had dismal yields — so bad that they are usually not even reported and dismal enough to eliminate the possibility of actually manufacturing devices using that method.

"One of the leading candidates recently published their yields . . . and out of 30 or 40 attempts to make a quantum dot only two or three actually worked at room temperature," said Berger. "It's a very daunting problem."

The biggest stumbling block, according to Berger, is the exceedingly small dimensions of the devices used to make a quantum dot. Individual devices can be hand-assembled using a scanning tunneling microscope, but even the highest-density manufacturing process, electron-beam lithography, is at least 10 times too gross for crafting quantum dots.

"You are trying to make devices that are smaller than what is attainable with all current lithographic techniques," Berger said. "To achieve room-temperature operation you need a quantum dot smaller than 4 nanometers, but that's still an order of magnitude smaller than even electron-beam lithography, which itself is not a high-throughput technology."

In addition, even the quantum dots that do work after fabrication do not evenly distribute themselves across a wafer. On the contrary, current work shows that working quantum dots tend to clump together in unpredictable locations. Other researchers are mitigating the problem by straining the surface of a wafer during fabrication or, alternatively, preparing the substrate for epitaxial growth with some kind of background pattern. According to Berger, however, even the most successful of these approaches only succeeds in getting working quantum dots to aggregate, not to spread out in an even, uniform array.

"Today, quantum dots form wherever they want to on a wafer, and there is no way you can wire up a complex circuit if your working devices are moving around on you from wafer to wafer," said Berger.

Berger's own work has been with resonant tunneling diodes, but other research team members have expertise in the other two popular approaches to building quantum dots — single-electron transistors and quantum cellular automata. All three of these architectures for quantum computing utilize the same basic principles in their use of quantum dots, Berger said. Like silicon devices, the dots can store their qubits either horizontally, next to their "gates," or vertically, below their gates, for even higher densities.

All the architectural techniques can be served by a common chip-processing technology, in Berger's view.

"We are not putting our eggs in any one of these future-architecture's baskets," he said. "All the future architectures are very similar, in that they all depend on the tunneling of an electron into and out of a quantum dot. We want to build a robust process that will reliably know where the devices are, predict their shape and reliably reproduce that shape across a large wafer, while still hitting the target of room-temperature operation."

The researchers will concurrently develop processing technologies that peg the size, shape and location of each quantum dot, thereby making the process suitable for mass production using present-day equipment. The fundamental techniques the team develops will be reported to the NSF's Nanoscale Science & Engineering Program, which amasses nearly $500 million in research grants in various nanotechnology areas, including both nanoscale device and system architectures.