Kevin Walsh, vice president of product management at Sequence, said the ShowTime static analyzer represents a next-generation timing in that it not only tool checks a chip's performance against requirements but also considers whether the physical effects of deep-submicron geometries start to influence chip performance.

Others are addressing this area. For example, Synopsys Inc. updated its marketshare-leading PrimeTime static timing analyzer with signal integrity issues and plans to add technologies accounting for more physical effects to PrimeTime in the coming months. Startup Incentia Design Systems Inc. also released a next-generation timing tool that accounts for signal integrity.

But Walsh claimed that ShowTime, with its inductance-modeling and IR-drop features, is raising the bar for static timing analysis tools.

"Inductance and power significantly affect performance once you drop below 0.18-micron," said Walsh. "Users have been requesting tools that give them a more-accurate account of these issues and they need a new sign-off tool."

Shashank Goel, vice president of advanced R&D and Fusion products at Sequence, said the tool includes six patent-pending technologies that allow the timing tool to account for signal integrity, inductance, resistance and capacitance and IR drop. He said it also offers an effective way to look at glitches and how they propagate to latches.

The tool was designed to work with commonly used Cadence and Avanti place and route flows and it can also be used with newer physical synthesis flows. The tool accepts standard formats such as Synopsys' .lib and Accellera's ALF (advanced library format). But, Walsh said, the company has added extensions to .lib to make it account for inductance and IR drop. ALF already includes these extensions. "We added extensions that account for how a glitch is going to be propagated across a gate," he said.

ShowTime users will begin working with the tool in the usual way, inputting libraries, netlist and design constraints, including the Synopsys Design Constraint format, Walsh said. But users will have to add information to calibrate the tool to account for noise effects to get the IR drop feature working effectively.

The tool produces a set of standard timing files along with information these other effects have on timing, and produces a list of glitch faults. The GUI allows users to view specific segments of their design where critical delays are occurring.

The tool also has a Spice-less stimulus feature. "We produce a conditioned Spice netlist, so not only will we give you the path but the potential victim path," said Walsh. "We will show and Spice-out the aggressor netlist and condition it so that it can be run in Spice easily. It will produce a netlist producing what we think is the bounded worst-case effect of whatever issue you are looking at — whether it is glitch or coupling delay."

Purnima Gauthron, product manager at Sequence, said the tool does not run slower than competing tools when running straight timing analysis. But since it accounts for inductance, IR drop and glitch propagation in one tool it saves a lot of user time because it does not require users to bring in other point tools to account for these effects in timing.

Gauthron said in a user design with 500,000 instances, it took one hour for ShowTime to complete the analysis. According to Gauthron, this customer said it would have taken four five-hour iterations using several tools to get the same results.

The tool starts at $40,000 for a one-year time-based license but the full version with IR drop, inductance modeling and other features runs $85,000 for a one-year license.

The basic Columbus-Turbo tool, with two CPUs, is priced at $87,500 for a one-year license. The top of the line version with eight processors is priced at $175,000 for a one-year license.