BY C. MICHAEL CHANG
President and Chief Executive Officer,
Verplex Systems Inc.,
Milpitas, Calif.

Within the electronic design automation market, the verification sector continues to grow. While we've seen some minor delays in purchasing and, in one case, a slight reduction in the original purchase order, we've not experienced the dire predictions that some sectors have reported. We've seen no impact on design starts, either.

We believe the bullishness of our market segment is due to the growing need to incorporate verification-or more specifically, formal verification-into the design flow. It's become a competitive advantage in many instances and a means to reduce overhead costs.

Formal verification, once viewed as an arcane technology that was not ready for mainstream design flows, is now seen as a valued productivity tool and a key piece of the overall strategic plan.

The move to a complete system-on-chip (SoC) enables more functionality in a smaller area. While that is a technological advance, it has forced companies to seek higher-capacity, faster and more thorough means of verification to handle the added complexity. Gone are the days of the "cobbled" approach-throw a variety of EDA tools and more engineers at the design and hope for the best. With verification estimated to take up approximately 70 percent of the design process, it's no longer realistic and certainly not effective.

Simulation by itself is no longer adequate for verifying SoC designs, because performance is slow and coverage is inadequate. Instead of applying stimuli to a design and comparing its responses with expected results, formal verification examines a design and mathematically proves its functional properties. Equivalence checking, part of a formal verification methodology, automatically detects functional inconsistencies, providing a reliable way to ensure that the final design implementation does what the RTL code specifies.

Formal verification is flexible and can be used throughout the design process. In design creation, it can show a design satisfies certain properties or can derive functional vectors to demonstrate the violation of such conditions. During implementation, it ensures that such design steps as logic synthesis, place-and-route, test-logic insertion and clock-tree synthesis do not accidentally introduce additional bugs. Finally, formal verification offers a solid return on investment. It enables design teams to concentrate at what they do best: design.

As always, tools that offer good value and productivity gains are often immune from economic downturn. I believe that's why our market segment has remained relatively untouched.

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