BY MIKE BAIRD
President,
Willamette HDL Inc.,
Beaverton, Ore.

During this economic downturn, the trend within electronics companies is to increase the productivity of existing design teams and prepare for the next upturn. As electronics companies impose hiring freezes that mean design teams cannot grow, or layoffs so that design teams shrink, shrewd managers are looking at how to get the most out of the teams they have left.

Electronics companies are increasingly concerned about productivity to enable them to compete effectively as the economy continues to constrain growth. As providers of design language training, we are seeing a greater interest in increasing productivity through the adoption of new techniques for functional verification or by making the move to system-level design. In the drive to greater productivity, we see a clear focus on the design team.

In our beginning Verilog and VHDL classes, we tend to see people sign up as individuals. The students are usually new hires, or individuals being cross-trained, and typically we see only one or two from each company in our regularly scheduled classes. Conversely, for our system-level language and hardware-verification language courses, we tend to have greater demand for on-site classes where we are asked to bring entire teams to proficiency.

These changes appear strategic in nature, and are being made to improve productivity and help companies weather the downturn.

Why are these design teams learning new techniques and languages? Our students tell us that they are making a change primarily for one of two reasons. Either they need a better way to address functional verification, or the combination register-transfer-level/HDL design environment is at its limit.

Many design teams are finding that RTL descriptions with HDLs are at or beyond their limit for handling the size and complexity of today's designs. They look ahead to tomorrow's designs and realize that their current methodology will not be adequate. Many SystemC students are exploring how to describe their designs at a higher level of abstraction to enable faster simulation, to enable hardware/software co-description and co-simulation, and to get their arms around the design.

In spite of the economic downturn, the complexity of designs continues to increase. Higher levels of complexity in today's and tomorrow's system-on-chip designs are forcing a move to new verification techniques and higher levels of abstraction to break through the simulation and verification bottleneck. The current slowdown provides an opportunity for companies to make the change.

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