Manufacturers of chip-scale packages are stacking devices two and three high in an effort to cram more functionality in less board space. At the same time, vendors are working to lower package profiles, especially for application in handheld products.

With footprints only about 20 percent larger than those of the chips they hold, chip-scale packages (CSPs) are bringing a raft of advantages to designers of small electronic devices such as MP3 players, handheld organizers, cellular telephones and digital cameras.

"For consumer products, pc-board real estate is a big concern, and designers want to put on as many components as they can. That's where a CSP becomes a requirement," said Abhay Maheshwari, senior manager of packaging technology at Xilinx Inc. (San Jose, Calif.). Wireless products, especially, are driving demand for CSPs from manufacturers serving Europe and the Asia-Pacific region, Maheshwari said. Xilinx offers chip-scale packages ranging in height from 1.1 to 1.4 mm.

Semiconductor houses and packaging vendors are introducing new CSP offerings. In May, Actel Corp. (Sunnyvale, Calif.) rolled out its eX family of field-programmable gate arrays in CSPs, cutting the board space taken up by the FPGA by 66 percent. The eX family is aimed at portable applications.

Also in May, the Electronic Device Group of Mitsubishi Electric and Electronics USA Inc. (Sunnyvale, Calif.) said it would offer 8- and 4-Mbit low-power SRAMs in 48-ball fine-pitch ball-grid array CSPs so that customers can migrate faster and more easily to higher-density products. Those devices will ship in volume later this year.

Chip-scale packages offer some of the advantages of flip-chip technology without the disadvantage of having to handle bare die; however, despite the fact that CSP I/O counts are rising, they remain in the low to medium pin range. Xilinx, for example, offers one CSP package for 48- to 56-pin devices and another for 144- to 280-pin parts.

"We don't have plans to go higher than that," said Alelie Funcell, Xilinx's vice president of supply management, engineering and manufacturing. "We can design a package with more I/O, but it would be a challenge for a user to lay it out on a board in a cost-effective manner."

Though single-chip CSP solutions remain the norm, vendors are paying more attention these days to stacked CSPs, also known as system-in-a-package (SIP) or 3-D packages. "Stacked packages can decrease total system costs by reducing the number of components and simplifying the design of a printed-circuit board," said Jon Woodyard, product manager for stacked CSP at Amkor Technology (Chandler, Ariz.). Stacking multiple die inside a package also reduces the length of the interconnections between the silicon, which results in better electrical performance at both the component and the system level.

Vendors are stacking multiple flash devices, SRAMs, DRAMs, microcontrollers, ASICs and DSPs into slim-line packages for designs that are sleeker and more compact, but also more complex.

"Stacked CSP is being hotly debated," said Bill Chen, senior technical adviser at Advanced Semiconductor Engineering Inc. (Santa Clara, Calif.). "On the one hand, you have people designing systems-on-chip, who want to put as many functions on a chip as possible. Then, on the system-in-package side, you have devices that are much more easily implemented, to let designers bring products to market faster. SIP has some real physical advantages on its side."

Advanced Semiconductor Engineering in May launched its Sandwich stacked-die CSP, which stacks up to three identically sized die in a 1.2-mm package. The device is intended for use in mobile phones, PDAs, digital cameras and other compact products.

Designers are using stacked CSP to double the amount of memory (such as flash or SRAM) in a product by putting two or more die in one package. They are also creating SIPs by combining both memory and logic chips. By putting several chips in a single package, assembly test and handling costs are reduced and the system size is shrunk.

Stacked CSP technology also allows designers to react quickly to competitors. "Engineers like the stacked CSP because it means that they can stuff more memory into the same-size package," said Narayan Purohit, vice president of Mitsubishi's Memory Division. "Although reliability has historically been a concern when stacking several chips, it has become a solid process because we are using basic memory chips in the CSP."

The most innovative moves in CSP have been toward thinner packages. Although 1.4 mm was once the standard, 1.2-mm packages are becoming normal and some manufacturers are starting to introduce packages as slim as 1 mm. "The direction in the industry has been toward a 1.4-mm standard until this year," said Amkor's Woodyard. "Now, most are starting to roll out 1.2-mm CSPs for stacked BGA and even talking about 1 mm." Amkor will offer 1.2-mm packages late this year or early in 2002, he said.

Amkor is already shipping its etCSP package, which offers a 0.5-mm maximum mounted height obtained thanks to a smaller solder-ball diameter and a thin-core laminate substrate. Conventional IC-processing techniques are used, including standard wire bonding, molding and substrate infrastructure. The resulting package consists of one or two peripheral rows of 0.3-mm-diameter solder balls to allow common SMT processing.

The etCSP also offers enhanced moisture resistance, according to Amkor. Since no die-attach materials are used to mount the die, chances of trapping moisture are reduced.

The etCSP packages can also be stacked after testing so that two mounted packages measure less than 1 mm. Amkor's package is aimed at PCMCIA cards, miniature disk drives, thin wireless handsets, flash or E2PROM memory, and other portable products where vertical height is limited. The company is currently shipping a two-chip version and has qualified a three-stack package that will be available in volume next year.

In June, ChipPAC Inc. (Fremont, Calif.) said it was beginning volume production on a CSP the same size as the die. Traditionally, vendors have offered "pyramid-stacked" solutions that put smaller chips on top of larger ones.

By contrast, "We've developed a process where we can put a spacer between the two die when the die on the top is same size or larger than the bottom die, so we don't crush the wires," said Marcos Karnezos, ChipPAC's chief technology officer.

"Last year, the package was 1.4 mm thick and by the end of this year we will achieve 1.2-mm thicknesses. In another year or two, 1 mm will be the norm."

Meanwhile, Tessera Inc. (San Jose) is working with Intel Corp. on a package that stacks three silicon die into a CSP less than 1 mm high. Aimed at next-generation wireless devices, the package uses what the companies call a "folded/stacked" technology that places the three die vertically in a single package.

In packages with conventional wire bonding, the spacer pads that provide clearance for the wire bonds increase the package height. Tessera's technology eliminates the need for spacers. "The die are produced side by side and folded over so the bond pads are independent of each other," said Craig Mitchell, vice president of Tessera's memory business unit.

Tessera's package uses patented technology to put a relieving layer between the chips to create compliance between the thermal expansion and the printed-circuit board. "Our package is very reliable because it can accommodate internal stresses," said John Riley, vice president of Tessera's wireless business unit. "Stresses go up as packages get smaller, but with less stress, you can use thinner die and smaller solder balls to attach it to the board."

First samples of the folded/stacked package have been shipped to Intel, and Tessera expects to make the package widely available before the end of the year. The company is also developing other stacked packaging technologies, some of which target baseband processors and other high-pin-count semiconductors. Those packages are also expected before the end of the year.

CSPs still cost more than traditional packaging options, but the premium can be mitigated by designers who use CSP technology effectively. "A lot of the cost for CSP is related to the fact that people haven't designed for the technology," said Daniel Mis, vice president of engineering applications and design at Unitive Advanced Semiconductor Packaging (Research Triangle Park, N.C.). "If you design for applications, the cost will go down and make it more attractive for other applications."

HAILEY LYNNE MCKEEFRY IS A FREELANCE TECHNICAL WRITER BASED IN BELMONT, CALIF.

---

Company Contacts

Actel Corp.
(408) 739-1010
www.actel.com
EETInfo No. 601

Advanced Semiconductor
Engineering Inc.
(408) 986-6500
www.aseglobal.com
EETInfo No. 602

Amkor Technology Inc.
(480) 821-5000
www.amkor.com
EETInfo No. 603

ChipPAC
(510) 979-8000
www.chippac.com
EETInfo No. 604

Mitsubishi Electric
and Electronics USA
(408) 730-5900
www.mitsubishielectronics.com
EETInfo No. 605

Tessera Inc.
(408) 894-0700
www.tessera.com
EETInfo No. 606

Unitive Advanced
Semiconductor Packaging
(888) BUMPING or
(919) 941-0606
www.unitive.com
EETInfo No. 607