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Sequence readies next-gen WattWatcher software








EE Times


SANTA CLARA, Calif. — Sequence Design this week will roll out a tool suite that represents the next generation of the WattWatcher software that it acquired along with Sente Inc. The PowerTheater suite includes Analyst, a full-chip dynamic power analyzer, and Designer, an advisory tool that recommends block-level changes to register-transfer-level (RTL) code.

PowerTheater represents the evolution of WattWatcher into system-on-chip design, said Kevin Walsh, vice president of product management. He said that Sequence will continue to support WattWatcher customers who are on maintenance, but expects the user base to upgrade to PowerTheater over time.

Separate offerings

WattWatcher did not have separate offerings for analysis and advice. "With PowerTheater, we're really putting the right tool in front of the right user," said Will Ruby, Sequence's director of product management for power. He said that Analyst will typically be used by "physically aware" designers to estimate full-chip power consumption at the RTL or gate levels, and that Designer will be used by RTL designers to reduce power consumption at the block level.

Ruby said Analyst has a number of features not available in WattWatcher. These include an ability to accept mixed VHDL and Verilog, support for multiple power supplies, a template library for intellectual-property blocks and an incremental compilation capability that lets users make small changes to RTL code without having to rerun the entire analysis.

Input to Analyst consists of RTL or gate-level netlists, activity data from RTL simulation and a power library. The preferred library format is Advanced Library Format, although the Synopsys .lib format is acceptable. The library may come from ASIC vendors, commercial suppliers or from the user's own CAD organization.

Analyst can handle "multimillion-gate" designs, Ruby said, and run-time depends on the length of the vectors used for simulation. He said RTL accuracy is typically to within 20 percent of silicon, and gate-level accuracy within 10 to 15 percent.

Analyst lets users view power consumption as a function of time. "As opposed to a single average number, we provide a waveform," Ruby said.

Designer claims to reduce block-level power consumption as much as 50 percent. It analyzes RTL code and suggests various power-reduction techniques, such as splitting a large memory into two smaller ones. Designer looks at all types of circuitry on the chip, including control, data path, I/O, memory and clocks. It has a simple built-in analysis capability and does not require Analyst to run.

For power-constrained designs, Ruby said, Sequence recommends running Analyst first to find hot spots, and then running Designer to reduce them.

The products are licensed separately, and will be available in September. Analyst starts at $135,000 and Designer at $65,000.











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