The task of navigating resolutions to the three major interface debates converging on network processors has fallen to the Network Processor Forum ad hoc industry standards group.

Though the NPF enjoys broad support from the 77 companies— most of them networking-chip vendors— that are its members, so many overlapping standards have been launched that territorial disputes have been unavoidable. And some are questioning how the NPF will tackle tough issues, such as devising a control plane interface, when interest groups backed by influential companies are already entrenched.

One factor working against NPF is its late arrival. The forum was created only this year, well after many of the I/O interest groups had already defined their specs. That has put the NPF in an awkward position: It wants to defer to existing standards when it can, but doesn't want to shy away from making changes that might better support Internet Protocol packet processing. Often, that will mean compromise, and whether the group can convince vendors to sign on is still a question.

Last week's Hot Chips conference underscored both the urgency of the task and the scope of the challenges that confront the NPF. Linley Gwennap, principal analyst for the Linley Group (Mountain View, Calif.), noted at a panel session that more than 30 network processor vendors are already using a variety of architectures (including multiprocessing, multithreading, very long instruction word and single instruction, multiple data). Design wins for the nascent chip category already exceed 400, and the chips are shipping now at OC-48 (2.5-Gbit/second) speeds, with OC-192 (10-Gbit/s) versions expected by year's end.

In the look-aside interface working group, which is defining a standard way of linking to SRAMs and content-addressable memories (CAMs), the rival quad-data-rate and Sigma RAM SRAM camps have been dueling for months. Recently, the working group tentatively settled on QDR as the baseline spec, but with some additional timing parameters proposed by the Sigma camp. A backward-compatible mode for pure QDR is also part of the spec, said Dave Gampell, director of marketing at Power X Networks and chairman of the NPF's education and marketing working group.

"We're going to try to tighten up the timing a little bit, in the way that Sigma does it," he said. "But everyone will understand you would be allowed to run in pure QDR mode in the look-aside interface, understanding that you're giving up some of the NPF [specification]."

But if the NPF adopts the spec early next year when it comes to a final vote, the effect could be tantamount to creating yet another competing standard. SRAM makers Cypress Semiconductor, IDT, Micron, NEC and Samsung, which back QDR, are unlikely to change course, because of strict rules requiring conformity to the existing spec. The QDR group also prohibits members from joining rival camps like Sigma.

Meanwhile, QDR is expected to expand its vendor base soon by bringing in Hitachi and is trying to persuade coprocessor and CAM vendors to adopt QDR, said Antonio Alvarez, senior vice president of the memory products division for Cypress.

Music's play
One of those companies is CAM vendor Music Semiconductors, which said it has adopted QDR for its latest 9-Mbit ternary CAM. Music, an NPF member, said it will likely adopt the NPF's look-aside interface, as long as that spec doesn't stray too far from QDR.

"I don't think we'd want to bastardize the QDR interface," said James Goodhart, director of product marketing. "We don't want to go back to our existing design base and tell them they have to re-lay out their boards."

Gampell said the NPF's goal is to make sure that doesn't happen. "The NPF version will be able to go back down to QDR so that anyone who adopts it doesn't have to rip up their board and re-lay it out," he said.

But this is just round one of the look-aside bus fight. Already, vendors are making pitches for look-aside 2, which could use a faster, differential-type bus with streaming characteristics. Gampell said the NPF won't tackle that spec until mid-2002.

The biggest battle yet to come could be over the control host interface, which would link a network processor to a general-purpose processor on the data plane. There, the Hypertransport and Rapid I/O camps are the leading contenders, and each group is digging in its heels.

"There will be vigorous debate, just like with QDR and Sigma," Gampell said. In the past some have tried to persuade Rapid I/O and Hypertransport groups to merge, but without success. "We had a lot of discussions to get some consensus. But the buses are not compatible," said Tom Riordan, vice president and general manager of the MIPS processor division at PMC-Sierra Inc., one of several MIPS-processor vendors that have backed Hypertransport.

NPF is expected to take on the host processor bus later this year but not to render a decision until next year. By then, many companies will have designs finished or in progress with either Rapid I/O or Hypertransport. "The problem is that everyone has their own territory staked out," Riordan said. "If they [NPF] pick one, they're going to make two out of three people mad."

"The control plane [debate] is going to be the hardest one," said analyst Gwennap. "The MIPS processor guys are behind Hypertransport, while IBM and Motorola are behind Rapid I/O. This is a case where two standards are really going after the same market niche. It's going to get ugly before that's resolved."

Moreover, the NPF may add its own tweaks for the control plane, just as it is trying to do with the look-aside interface. Gampell sought to reassure vendors that "all we're really doing here is taking stuff that's out there and leveraging and tweaking it [for IP] packet processing, without any undue burden on vendors supporting existing standards."

Consensus has been somewhat easier to achieve for the so-called streaming interface to the switch fabric. As of now, the existing Common Switch Interface (CSIX) standard backed by NPF must be widened to 64 bits and increased to 250 MHz for vendors to move to OC-192 rates. That's tough for chip vendors to swallow, because they will have to add pins to devices that already can have 1,000 pins or more.

To get around that problem, the NPF hopes to bring in an overlapping spec that would send the CSIX protocol over an SPI 4.2 physical interface, which can enable speeds of OC-192 and above using a narrower, 16-bit interface for both directions. To compensate for the additional overhead of net processors, NPF has proposed to speed the SPI-4 wires so they run at 1 Gbyte/s for each pin.

"There's a lot of momentum behind this [SPI-4.2] fabric interface," said Gwennap.

Silicon vendors that want to be among the first to offer OC-192 devices are still expected to use the wider version of the CSIX physical interface. The SPI-4.2 streaming spec is not expected to be formally ratified till February.

"A lot of companies are trying to tape out 10-gig network processors in the next six months," Gwennap said. "That date is coming up hard on companies that are ahead. They can't wait for the standard to be resolved."

Protocol issues
While the physical interface to the fabric appears to be settled, IC vendors are still arguing over protocol issues like flow control, which varies widely from vendor to vendor. "There aren't preexisting standards with snappy marketing names. People have developed their own ways of doing flow control," Gampell said.

Several companies plan to provide bridge chips for competing standards such as Rapid I/O and Hypertransport. And programmable-logic makers like Altera and Xilinx are rushing to capitalize on the spec wars.

But only so many I/Os and physical interfaces can be absorbed by users and supported by PLD vendors. "Customers see these standards overlapping to a certain extent," said Craig Lytle, vice president for intellectual property at Altera. "I'm confident there will be some fallout."