Because DRAM performance has not kept pace with logic speeds, chip processor vendors have stuffed their designs with bigger cache memories. But some say processors are reaching their limit in how much extra performance they can derive from bigger cache, particularly in networking applications.

For its part, Motorola added a larger 256-kbyte Level 2 cache and strapped on an Level 3 cache to its latest G4 PowerPCs, which run as high as 867 MHz. In the future, however, the company wants to avoid integrating more cache onto the processor. "It would be a huge cost in die size," said Raj Handa, manager of the PowerPC products platform division.

Rather, Motorola is looking into adding a memory controller to the PowerPC, though the company hasn't specified which derivative. By doing so, the processor could bypass an external bus and have a direct link to the DRAM.

"It makes a lot more sense to add high-speed memory controllers on processors," Handa said. "Anytime you have a bus, you have to arbitrate for the bus. Rather than let it go hungry, you could feed the processor as fast as it can be fed."

Handa cited double-data-rate (DDR) SDRAM running at 266 or 333 MHz as memories that could have a direct pipeline to the processor, but he declined to say specifically what kind of DRAM Motorola would consider. He said RDRAM "is not in the markets we play in, at least not today."

Motorola has experience integrating DRAM controllers into its PowerQuicc line of PowerPC-based processors for embedded Ethernet and ATM applications. But bolting on a high-speed DRAM interface to its monolithic high-end PowerPC line would be a first — and another step down the path toward gearing the architecture more for networking, where memory latency is considered a performance killer.

Several years ago, Motorola added the networking-oriented Altivec instructions to its PowerPC, and lately the company has been positioning the device as a control-plane processor working in tandem with its C-5 network processor. It has also been courting high-profile networking OEMs such as Cisco Systems Inc., which recently said it would use the highest-performance MPC7450 PowerPC in its next-generation routers.

Following suit

Companies designing the newest breed of network processors in particular have been quick to integrate DRAM controllers on their devices. Denali Software Inc., which helps design memory subsystems for chip designers, has worked with about a dozen network processor companies to integrate a DRAM controller onto their designs. Most recently, it announced that Clearwater Networks Inc. licensed its Databahn hardware and software tools so it could hook its processor to 300-MHz DDR SDRAM.

Some say this is because cache memory is hitting a wall. Cache memory is useful for speeding memory access in compute-centric applications because it stores data or instructions that can be re-used or that are in close proximity to a previous access. But packet data is more random, and the advantage of cache memory erodes in networking applications, said Kevin Silver, vice president of marketing for Denali.

"With cache, you rely on predicting what you need next. With packets, there's no predicting," Silver said. "Networking applications require more-specialized memory systems to achieve high bandwidth and low latency."

It was the need for low latency that drove network-processing chip company PMC-Sierra Inc. to attach a DDR DRAM controller on to its RM9000, its latest device that integrates two MIPS processors. PMC-Sierra had also added Level 3 cache to its previous RM7000 line but saw moving to a direct memory interface as a natural next step.

"Once you have L2, you've already got most of the advantage of the memory hierarchy that you can get," said Tom Riordan, vice president and general manager of PMC-Sierra's MIPS processor division. "If memory is really far away, then L3 can be effective. But once you integrate the memory controller, you've cut down the latency to memory by integrating and you can now get rid of the necessity for the L3 cache."