JHDL provides an alternative to both conventional HDLs and C/C++ design methodologies pursued by commercial EDA vendors. Advocates say Java is easier to use, debug and synthesize than Verilog, VHDL or C.

JHDL has displaced all other EDA tools at the BYU lab, where it's used to generate data path modules for Xilinx's 4000 and Virtex FPGA devices. A key JHDL feature is a user interface that serves both simulation and hardware execution. As of today, however, in the absence of behavioral synthesis, design entry is at the structural level.

"With the Xilinx 4000 technology, there are a lot of multipliers required, and we found it was just downright painful to do a good job of placement using VHDL," said Brad Hutchings, director of the lab and an associate professor of electrical and computer engineering at BYU.

"We tried a number of CAD tools, and they didn't work out," Hutchings said. "So we tried Java. When we did that, we could get module generators up and running much more quickly, and it was easier to debug them."

While JHDL has been used almost exclusively in academic environments to date, it's drawn some interest at Xilinx, said Steve Guccione, staff engineer at Xilinx (San Jose, Calif.). "I've seen JHDL and I think it's a nice design tool with some really nice integrated debugging features," he said.

"Personally, I'm a fan of Java," Guccione said. "There's a lot of emphasis on C these days, but I just think Java is a cleaner language that fits more easily into the hardware world." Guccione said he thought JHDL could be commercially viable. "I've heard nothing but good things from people using it," he said.

Xilinx stands as an exception to major EDA vendors that have so far shown little interest in Java. Last year Xilinx purchased LavaLogic, the developer of Forge, a Java-to-Verilog compiler. Xilinx intends to integrate Forge into its tool flow and to offer both C and Java front ends to the compiler. Forge is currently available from Xilinx as part of a beta release program.

Java advantages

Hutchings calls himself an ardent Java fan. Compared to VHDL or Verilog, he said, Java is a general-purpose programming language that's easier and faster to use. It also has a lot of support from standard compilers and debuggers, he noted.

And Java has some key advantages over C/C++, Hutchings said. "What I've noticed, and what many of my colleagues have noticed, is that when we have students write in Java, they write more quickly and their code tends to have fewer bugs," he said. One reason, he said, is that Java's "garbage collection" prevents memory leaks that might arise in a C language program. Another Java advantage is portability.

Java is easier to synthesize, Hutchings said, because it avoids "aliasing" problems that might occur with C. Such problems can occur when different pointers are trying to access the same memory block.

Hutchings said that BYU students use Java objects to represent hardware concepts like wires and ports. Concurrency isn't a problem today, he said, because JHDL currently takes structural descriptions. The forthcoming behavioral synthesis capability will represent concurrency with Java threads.

As it exists today, JHDL includes a library of data path modules, a graphical debugging tool that supports both simulation and hardware execution, a schematic generator, an EDIF 2.0 netlist class, and EDIF parser, simulation models for Annapolis Microsystems Inc.'s WildForce platform, and a state-machine generator. A graphical floor planner is currently under development.

The tool converts Java to an EDIF netlist that can be fed into Xilinx placement and routing tools. It could potentially support other reconfigurable architectures in the future, including non-FPGA platforms such as those from Chameleon or Morphics, Hutchings said.

Debugging capability

Hutchings said he is particularly proud of JHDL's debugging capability, which supports both simulation and hardware debugging. "By just pushing a button on a dialog box, you go into hardware mode," he said. "All the tools you use in simulation — such as tools for examining and changing values, and single stepping — are available. It's a unique capability not in any tool I'm aware of."

Users can also run the debugging for 100,000 cycles or so, and then dump the state of the system, he noted. Later on, they can go back with a simulator to explore problems further.

Even though the design entry is currently at a structural level, the code is compact, Hutchings said. "All it is, is function calls to data path module generators," he said. "That makes it pretty easy to get to a million gates."

Aside from the lack of behavioral synthesis, the current generation of JHDL does have some limitations. For example, even though it can handle an arbitrary number of clocks, it doesn't allow asynchronous loops. "It's not a fundamental limitation," Hutchings said. "I just ran out of students."

Hutchings said that BYU will offer "pretty much everything we've got" with JHDL on an open-source basis within a month or two. As of now, the executables are available, along with documentation, at www.jhdl.org. Hutchings said most of the use has been academic, although several small companies have expressed interest.

"I think it's very commercially viable," Hutchings said. "We're already doing high-performance circuits with a million or more gates. Our simulation time is as good as anything out there, and our hardware debug capability is unique.

"Users have said, 'Just form a company, we'll buy it.' I'm not a business person, I'm an academic. I don't know quite what it would take to commercialize it. But it sounds like it would probably do okay."