Gary Smith, chief EDA analyst with Gartner Dataquest, called the alliance a "good, solid technology play," making the SPC-Plato flow a contender for next-generation physical design. The link-up thrusts the two companies into competition with the likes of Avanti, Cadence Design Systems, Magma Design Automation, Monterey Design Systems and Synopsys.

"Possibly they could start picking up some of the Avanti seats, which would give them some momentum before the Cadence Integration Ensemble is out," Smith said. "But they still don't have a synthesizer, so they don't have the whole flow. The question is whether customers will want to pick up a tool set that doesn't have a synthesizer."

Smith noted, however, that Silicon Perspective's First Encounter has taken the lead in silicon virtual prototyping, replacing Synopsys' Chip Architect. And he said that Plato's Nanoroute appears to be "a next-generation router." First Encounter isn't used today for final placement, but with the addition of Nanoroute it could take this role, Smith said.

When the Silicon Perspective-Plato flow is solidified in December, users will be able to create a full-chip physical prototype with First Encounter, performing hierarchical clock tree synthesis and power grid design at the chip level. They will perform synthesis with Synopsys' Physical Compiler and do placement and in-place optimization with First Encounter at the block level. Users then, at the chip level, can use Nanoroute to perform a top-level route; at the block level, they can use it for detailed routing.

Over the last year, First Encounter and Nanoroute have independently garnered great praise from the user community, netting their makers a substantial number of design wins.

"We both have very powerful tools," said Michel Courtoy, vice president of marketing at Silicon Perspective (Santa Clara, Calif.). "So creating a flow where they work together seamlessly makes them even more powerful." Courtoy declined to say if there are any plans on the table to eventually merge the two companies.

"This agreement was driven by user demands," said Joe Xi, vice president of marketing at Plato (Santa Clara). "We have several customers that have both our tools — who think Silicon Perspective has the best placement and we have the best routing — and want to be able to use them together."

Both tools have the capacity to handle 10 million-gate-count designs flat, Xi said, along with a hierarchical capability that allows them to handle 100 million-gate designs.

"Most people today are doing 6 million-gate designs and tools can handle them," he said. "But they have to look into the future where they are doing 100 million-gate designs on new processes. We have the only tools that handle designs this size."

In a tapeout report conducted in December by EDA industry watcher John Cooley, moderator of the E-Mail Synopsys User's Group, Silicon Perspective boasted 43 tapeouts, trailing only Synopsys' Chip Architect plus Flexroute, with 65 tapeouts.

And in Cooley's Design Automation Conference 2001 survey, users came forward to praise Plato's Nanoroute. Two anonymous designers showed benchmarks in which Nanoroute beat Avanti's Apollo router in run-time, capacity and memory utilization hands down.

Avanti, however, is downplaying the threat of a joint Silicon Perspective-Plato flow. "There is a critical synergistic relationship between placement and routing for all aspects of design closure," including timing, power, crosstalk and congestion, said Michael Jackson, head of Avanti's Design Products Division. "Bringing together independent placement and routing capabilities won't work well for [ultradeep-submicron] designs. Astro and Apollo have integrated placement and routing. Silicon Perspective and Plato don't."

Yet Austin, Texas, chip maker Banderacom said it used the Silicon Perspective-Plato flow recently to complete a 4 million-gate system-on-chip.

In a press release issued by Silicon Perspective and Plato, Banderacom reports that the flow required only 2 Gbytes of main memory on a single 32-bit workstation for a 4 million-gate design.

For the same number of gates, the company said in the release, competing place-and-route solutions, with their memory-intensive databases, required 6.8 Gbytes of main memory on an expensive 64-bit workstation.

A Banderacom spokesman went on to say that with a single CPU, run-times for place and route were three times faster in the SPC-Plato flow than in traditional solutions. This ratio improved to 5x with two CPUs.

The Silicon Perspective-Plato combo was used in the design flow without any additional tools for placement or signal routing, Banderacom said. However, the company had to employ tools created by Mike Stabenfeldt's one-man Austin-based operation, Stabie-Soft, to fill holes in the flow. Stabie-Soft provided power-routing technology to Banderacom to fill a hole in First Encounter and also supplied the technology to enable Plato's Nanoroute to generate "GDSII-out," the company reported.

But Courtoy said that Silicon Perspective is currently developing its own power grid design solution and that Plato is devising its own GDSII-out technology. He said the holes should be filled and the complete flow ready from Silicon Perspective and Plato by the end of the year. In the meantime, users can obtain the filler software from Stabie-Soft.

Richard Goering contributed to this article.