While Xilinx may be bucking the conversion trend, vendors of gate arrays and metal-layer programmable devices are devising plans to lure communications OEMs that are scrambling to slash systems costs as they climb out of the rubble of the telecom market crash. That's pressuring FPGA suppliers to offer alternatives to pricey programmable devices, sparking a new life for FPGA-to-ASIC conversions.

Downsizing and layoffs at companies like Nortel and Cisco, traditionally big users of programmable parts and ASICs, have put pressure on those OEMs to reduce their bill-of-materials costs. That has prompted a surge of interest in devices that can be programmed in the factory within weeks, with lower nonrecurring engineering costs than for cell-based ASICs and more attractive unit pricing than for FPGAs.

Various suppliers are moving in to fill the void left by Xilinx's departure from the conversion business. Lightspeed Semiconductor is coming out with its own mask-programmable gate arrays, complete with on-chip test and debug features, that are offered with the same memory and pin configurations as Xilinx's Virtex E FPGAs.

Meanwhile, Clear Logic in coming weeks will announce a family of Altera-compatible devices that are said to be less than half the size of a similar Altera part and to be programmable using an FPGA bit stream.

At the same time, American Microsystems Inc. is preparing to roll out its most advanced, 0.18-micron process FPGA-to-ASIC conversion, which will target high-end devices from both Altera and Xilinx. Gate array vendor NEC Corp. gave its own program a similar shot in the arm when it announced 0.25-micron devices earlier this year.

While the general semiconductor market remains mired in the doldrums, many companies looking to offer FPGA conversions say they've seen a spurt of new orders in recent months.

Don Knowlton, vice president of marketing for Clear Logic (San Jose, Calif.), said one large communications OEM had turned the company down twice but has recently grown more receptive. "By the third time, they told us not to bother giving the presentation, and we thought we were out again. Instead, they said, 'We decided we're going to use you,' " Knowlton said.

Other vendors have taken note of the attitude shift. Last year was a big year for FPGA conversions for AMI, but most orders were limited to the priciest devices. In recent months, the company's requests for conversions have shot up 30 percent. "It's not just one or two here and there. We're seeing multiple designs at a time for customers. It was less of a large-scale approach in the past," said Vince Hopkin, vice president of the Pocatello, Idaho-based company's digital ASIC division.

Gate arrays and FPGA conversions are gaining ground largely because systems vendors are paying more attention these days to bill-of-materials costs, observers said. "There's significant price pressure on systems vendors. They have to go to production in a way that's more affordable," said Dave Holt, president and chief executive officer of Lightspeed (Sunnyvale, Calif.).

Overall, the revenues generated from gate arrays are expected to decline this year, perhaps as much as 22 percent. But there is still money to be made in wooing customers that don't fit neatly into FPGA or cell-based-ASIC vendors' business plans, said Bryan Lewis, an analyst with Gartner Dataquest.

"The reality is that in 2001, it's still a $2 billion to $2.5 billion market. That's a nice piece of change," he said. "There is still a gap that is not being serviced well. If you're a second or third-tier customer and PLDs are not fast enough and the ASIC guys won't give you the time of day, what do you do?"

Big customers, too

And it's not just the little guys who are asking for a migration path from FPGAs to ASICs. Altera said its mask-programmable program is intended to curry favor with large customers like Nortel and Motorola. The company believes the potential benefits outweigh its concerns about cannibalizing its core PLD business with devices that will cost one-fifth as much as FPGAs.

"We're going to do these conversions for a pragmatic reason: We'd like to keep that business," said Cliff Tong, vice president of corporate marketing for Altera (San Jose).

Cross-town rival Xilinx, however, dismissed Altera's strategy as an opportunistic bid to amass socket wins at the expense of sound business practice. Xilinx years ago moved into FPGA-to-ASIC conversions, but it abandoned the program in late 1999 because of exorbitant costs and technical problems.

Xilinx ran into timing problems when it moved to its more complex Virtex line of FPGAs. Often it could only meet timing parameters 60 or 70 percent of the time when making conversions.

"You're talking about two fundamentally different technologies," said Shelly Davis, marketing manager for Virtex group, who oversaw the conversion program. "There were times when you couldn't even meet the timing in the I/Os. And there was so much RAM in these devices that we were blowing the die up, because the gate array process is inefficient for RAM."

Another problem was that only one in five customers actually moved its devices into volume production. "We were dumping hundreds of thousands of dollars into the designs before we knew if they were going into volume. Then we were stuck," Davis said.

Altera's Tong countered that the company is making a significant investment in mask-programmable devices for the long haul. In many cases, timing should improve, because the mask-programmed devices do without the routing overhead of FPGAs. Other timing problems can be addressed through patented technology improvements.

"I'm not saying this is a straightforward, cookie-cutter thing, but you can do it," Tong said.

AMI's Hopkin said Xilinx failed because it waved too many customers into its hardwired conversion program without holding them to volume production. He acknowledged that timing is difficult because customers often use asynchronous designs with multiple clocks. Even so, AMI claims it can get it right 95 percent of the time with its vector coverage and timing verification.

Other companies are looking to piggyback on PLD vendors with conversion programs. Clear Logic in coming weeks will announce a 50,000-gate architecture that uses reverse-engineered logic structures said to be functionally equivalent to and pin-compatible with Altera's Flex 10K50V FPGAs. Clear Logic claims its laser-programmable devices consume 60 percent less die area than an equivalent Altera FPGA. With the new offering, the company switched to a new vertical fuse structure, which narrowed the spacing between metal lines to reduce area by 30 percent.

The Liberator family also has embedded test capabilities so that test vectors are not needed. The company promises to deliver prototypes five weeks after receiving an order, with no NRE charges, said Knowlton of Clear Logic.

Lightspeed Semiconductor, meanwhile, is looking to undercut Xilinx in a similar manner. The company has started taking orders for its 4Em "modular array" ASICs, metal-mask programmable devices that use the same BGA packages as Xilinx's Virtex E and identical memory configurations. The family is available in versions ranging from 250,000 to 1 million usable ASIC gates and includes built-in test and debug capabilities and IEEE 1149.1 boundary scan for I/O test. Prototype turnaround requires three weeks after netlist sign-off, but the volume price is about 80 percent lower than for equivalent Xilinx devices, the company said.

Routing is done in the metal and does without the extra capacitance of pass transistors used in FPGAs, making the architecture typically two times faster than FPGAs, said Lyle Smith, chief scientist for Lightspeed.

AMI, meanwhile, is getting ready to roll out what it believes is the first 0.18-micron gate array process that aims to give customers a conversion path for Altera's Apex 2 and Xilinx's Virtex 2. The process is aimed at designs with less than 2 million gates. "Right now we're extremely focused on Apex and Virtex," Hopkin said. "Demand for conversions has increased because cost reduction is such a huge issue this year."

Clear Logic-Altera suit

Still, FPGA vendors aren't making it easy for their customers to jump the fence to third parties, especially when intellectual-property (IP) rights are involved. Clear Logic, for one, is embroiled in a lawsuit with Altera over alleged misappropriation of Altera's mask technology, a claim that Clear Logic disputes.

The transfer of intellectual-property cores can also get dicey if another vendor is involved. "Realistically, we're the only people that can do this, in a sense, legally," said Altera's Tong. "We don't eliminate the possibility of going to an ASIC supplier; however, there is going to have to be licensing negotiations to use our IP in an ASIC."

Indeed, observers said even if a core is licensed from an FPGA vendor, the core may not be legally transferable to an outside ASIC supplier. Often, a company that specializes in FPGA conversions will have to duplicate the work of the programmable-logic vendor. "Either you have to have the same IP license or you have to develop an equivalent core," said AMI's Hopkin. "For example, Xilinx has a PCI core that they developed, so we went off and developed a functionally equivalent core."

One way around the licensing issue would be for an FPGA vendor to strike a partnership agreement with an ASIC maker. Xilinx is already working closely with leading ASIC vendor IBM Microelectronics to develop a customized PowerPC core for its Virtex device, but the relationship stops there.

When asked whether the two companies are extending the relationship to include common software or translations, Xilinx's Davis demurred. "We are always investigating this stuff, and we're always looking for new avenues," she said. "We do have a few tricks up our sleeves for customers that need cost reduction.

"It's not going to be anything like a hardwired conversion."