Columbus-RF is intended to be integrated with Cadence Design Systems' Analog Artist Design environment. Within a high-frequency IC design environment, the tool is used to extract interconnect resistance, inductance and capacitance (RLC) from a layout. With increasing demand for RF and optical-network ICs, the projected market is 1,200 seats, or roughly 10 percent of the Cadence-based IC design population, Walsh said.

Committed users of the tool, which debuted in its initial version at the Design Automation Conference last June, include IBM Microelectronics, Qualcomm, Valence Semiconductor and high-speed instrument manufacturer LeCroy.

However, the new version of the tool, introduced this week, allows easier parasitic extraction and faster computer simulations. It automatically finds the "return path" for loop induction, Walsh said. Other extraction tools would assume that the substrate of the IC represents the return path for an inductive loop created by surface metal traces, he said, but that is not always accurate.

The tool will find the inductive loops by examining the spacing between traces and calculating the loop inductance for the more closely spaced trace wires.

Another new feature, geometric reduction, is especially important for simulation speed. It reduces the netlist size without interfering with the physical integrity of the design, the company said. Thus, Columbus-RF, which effectively represents RLCs as "lumped loads" to Spice or Spectre circuit simulators, can compete in both speed and accuracy with meshed field solvers, which depend on detailed extractions from 3-D interconnect structures.

An additional feature — a consequence of the Cadence environment that permits a schematic and layout probing and simulation on one screen — is point-to-point probing. This not only makes the extraction of critical nets much easier for IC designers but also enables parasitics to be extracted and back-annotated into the schematic and layout.

Columbus-RF uses a subset of Standard Interconnect Performance Parameters from the Silicon Integration Initiative standards organization to describe the silicon fabrication process variables, Walsh said. Using this standard model description, design engineers can program their process-related information into the system. Columbus-RF automatically generates all the library information necessary to extract RLCs, accurate on 95 percent of nets within ±5 percent of standard field solvers like Quickcap and FastHenry, whose run-times can be 10 times as long, Sequence said.

Silicon foundries like Taiwan Semiconductor Manufacturing Co. will be able to extract and provide accurate process models and design kits for their RF and high-speed IC cells using the Columbus-RF tool, Walsh said.