world phone, with multiple frequency bands and multiple air interfaces, presents a broad set of challenges–both economic and technical. World phone devices of the future must be small, lightweight, and feature-rich, with extremely low power consumption. Furthermore, users of these devices are demanding more sophisticated feature sets, which in turn require tremendous amounts of additional computing resources. In fact, the mythical "killer apps" that a 3G worldphone must support have yet to be defined, resulting in a ripple effect on design cycles, time-to-market, costs, and product obsolescence.

Existing design methodologies and conventional integrated circuits–microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), and field programmable gate arrays (FPGAs)–make it difficult for designers to keep pace with today’s 2G requirements for handsets. Designers will face significant increases in design difficulties with the emergence of 3G technologies–not only for protocols, but also for software-defined radio (SDR), high-speed data, GPS/E911, true handwriting, and speech and visual recognition. The challenge for designers of the future worldphone is to provide the needed application mix within the area between the two curves of maximum allowable silicon and maximum allowable power dissipation.

The key problem is that conventional ICs and design tools are based on "rigid computing" techniques that rely on the use of rigid hardware resources and/or rigid algorithms. What is needed is a new breed of IC with a flexible architecture that changes on demand to access any number of protocols and standards, enable SDR, and to perform numerous functions –all at high speed, with low power consumption, reduced silicon area, and at low cost.

The solution lies in the Adaptive Computing Machine (ACM), a new class of IC, which is able to deliver these needed attributes while outpacing the performance of conventional IC technologies. Based on adaptive computing technology, the ACM provides an architecture that uses CMOS silicon more efficiently, achieving the levels of computing performance today that Moore’s Law forecasts out in time.

Adaptive computing is a revolutionary new method of computing in which algorithms are directly mapped onto dynamic hardware resources, resulting in the most efficient use of hardware in terms of cost, size (silicon real estate), performance, and power consumption. The capability of a wireless device is defined not by the IC embedded in it, but by the I/O surrounding it and the binary file used to program/configure it.

The complexity associated with the various technology generations for wireless standards is shown in Figure 1 in terms of MOPS (million operations per second) requirements.

Further complicating the matter is the lack of a single worldwide standard and the non-harmonized band allocations around the world. It is foreseeable that an operator would require a phone capable of operating in a variety of standards such as ANSI-136, GSM, GPRS, EDGE, cdma2000, and W-CDMA, with additional capabilities such as GPS, Bluetooth, and IEEE 802.11, over more than six different frequency bands. As wireless technologies move beyond 2G into 3G and 4G, they are becoming extremely complex, requiring much higher processing power than before.

For example, the wideband CDMA technology (W-CDMA), at 5 MHz bandwidth, requires chip rates of about three times its narrowband counterpart, TIA/EIA-95. This realistically translates into signal processing requirements that are more than an order of magnitude greater between 2.5G and 3G. The higher chip rates also mean that more multipaths will be resolved and, therefore, more rake receiver fingers may be necessary to coherently combine the received multipath energy. This can increase the ASIC processing requirements even more. Moreover, the high data rates enabled by the 3G technologies translate to higher symbol-rate processing as well. To further complicate matters, the higher processing power demands come with the requirement for low power consumption.

Consumers’ expectations for a worldphone are based on their PC and Internet experiences. This means consumers expect immediate access to a choice of protocols, standards, services, functions, and media-rich applications in a single wireless/mobile device. As the marketplace moves to 3G and beyond, software-defined radio will play a pivotal role in revolutionizing wireless communications, making these expectations a reality.

SDR is an enabling technology for wireless communications in several ways:

• Improving network performance;
• Enabling worldphone capabilities with seamless roaming throughout the world;
• Enabling large amounts of data to be delivered effortlessly to the mobile terminal;
• Improving device performance, whether stationary or mobile;
• Establishing new customers in domestic and global markets;
• Creating new revenue models for carriers, service providers, and handset manufacturers;
• Creating new businesses for new applications, such as video streaming.

However, the goals of SDR pose significant challenges for designers of next-generation wireless devices in the consumer space. The military markets currently experience the benefits of SDR, but in that environment, they’re able to use bulkier, sturdier devices that allow for using a chip per protocol (standard) or function. While this is a typical implementation when using conventional IC technologies, the associated cost and power consumption are not palatable in the commercial marketplace. What is needed to enable SDR in a commercially viable worldphone with extreme performance and flexibility?

One approach is to use more fixed-function silicon (FFS) in the form of ASICs. For example, a design team could use multiple FFS accelerators, each targeting a different task, such as a different interface standard, communications protocol, modulation scheme, data format, etc.

It would certainly be possible to create a worldphone that works anywhere in the world using this technique. However, in addition to being horrendously expensive, the resulting wireless device would be extremely large and power-hungry. Furthermore, ASICs employ a rigid IC architecture that is difficult and costly to change during the design cycle and is frozen once the design is completed. This means that such a state-of-the-art-super phone could not accept updates to accommodate rapidly changing communications standards, essentially making it obsolete at design time.

Every IC implementation technology has its own advantages and disadvantages.For example, an algorithm implemented in hardware–as in an ASIC–can run thousands of times faster than an equivalent software representation executed on a general-purpose microprocessor or DSP. However, the software implementation can be modified relatively easily, while the hardware version is effectively "set in stone", or in this case, silicon.

To evaluate the capabilities of these ICs, it is necessary to compare their flexibility, area requirements, power consumption, and computational throughput.

Note that flexibility is defined as a combination of programmability and adaptability. Programmability is the ability to use software to drive existing hardware functions in fixed-function silicon (ASICs, microprocessors, and DSPs). Adaptability is the ability to rapidly modify the silicon to perform a new or different function than was originally intended when the IC was designed.

For example, microprocessors and DSPs are highly programmable but not adaptable. FPGAs aren’t programmable, but they are reasonably adaptable, albeit at relatively low speeds as compared to ACMs. ASICs are not programmable or adaptable because their logic is "frozen in silicon." In fact, only ACMs are both highly programmable and adaptable.

Figure 2 is based on performing a single algorithmic function, of which all portions are required to be resident in hardware at the same time. In this case, an ASIC offers the optimal IC implementation in terms of silicon area, low power consumption, and high computational throughput.

However, the picture becomes more interesting when we consider a wireless, multi-band, multi-mode, multifunction (M32) device. In this case, we’re looking at a complex function with myriad algorithmic components. Furthermore, only a subset of these algorithmic components needs to be resident in hardware at any particular time. In fact, the only IC implementation technologies that satisfy the processing requirements of a wireless M3 device are an ACM and an ASIC/DSP hybrid.

The ASIC/DSP hybrid is reasonably efficient in terms of area, power consumption, and computational throughput. However, while a DSP is highly programmable, the combination of an ASIC and DSP is not. Coupled with the fact that neither ASICs nor DSPs are adaptable, this means the ASIC/DSP hybrid has very low flexibility. By comparison, an ACM is highly flexible, because it is both highly programmable and adaptable. This flexibility allows the ACM to be adapted "on-the-fly" to accommodate new, different, and ever-evolving interface standards, communications protocols, frequencies, modulation types, and data formats.

The vast majority of current wireless communications devices use a mixture of FFS accelerators and DSPs or microprocessors. The alternative is to use adaptive computing technology. In this case, our example world phone can be based on a single ACM. The architecture of the ACM is specifically designed to allow software algorithms to be directly converted into dynamic hardware resources. An ACM can be adapted "on-the-fly" to accommodate different interface standards, communications protocols, frequencies, modulation types, and data formats. Furthermore, because of the ACM’s adaptive architecture, an ACM-based device can accommodate incomplete or evolving industry specifications.

To quantify the improvements that can be expected from an ACM, several benchmarks have been created. These benchmarks compare the performance (power consumption and processing power) of an ACM against a typical DSP processor (dual MAC), for common, yet time-consuming functions, such as a FIR filter, an IIR filter, and a W-CDMA rake receiver. The FIR filter is chosen because the DSP is designed to perform that function very efficiently.

Each of the benchmarks started with the basic algorithm in C code. For the DSP, the C code was then translated into assembly. This translation was done by hand to ensure maximum efficiency. The power consumption and processing power requirements were then simulated for both 1.8-V DSPs and 0.9-V DSPs.

For the ACM, on the other hand, the C code was first translated into QuickSilver’s Q Language. Q is a derivative of C++, and allows for the scheduling and parallelization of operations. The Q code was then compiled into an internal data representation (a data flow graph), which was then scheduled. The scheduling process consists of allocating just-in-time resources (computing elements) to the different functions. The resources available for these benchmarks were limited to a very conservative number based on what can reasonably be expected from the architecture of an ACM. The silicon size for FIR and IIR examples were taken to be 1.1 mm2, while that of the rake receiver was 1.59 mm2.

After scheduling, the SilverWare (the binary code) was generated and downloaded into the ACM, bringing into existence the exact hardware as specified by the dataflow graph. The result is software that becomes hardware - rapidly changing its architecture and thus maximizing efficiency and processing power. In this benchmark, the ACM was based on 0.9 Volt, 0.18 micron CMOS process. The dataflow graph is shown in Figure 3.

In a similar fashion the assembly code and the dataflow graph for the IIR filter and the eight-finger rake receiver were generated. The rake receiver is more complicated, and as we will see, this leads to an even greater performance improvement than was seen with the FIR and IIR.

Table 1 summarizes the findings. The results were independent of silicon technology and process. It is clear from the table that the ACM can reduce power dissipation by at least an order of magnitude. Instead, the ACM can increase the processing power by at least a factor of four for simpler algorithms (FIR, IIR). The processing power is improved even more dramatically with algorithmic complexity (58 times better for rake receiver).