Packaging schemes that combine flash and SRAM memory chips in varying densities have become standard, but now companies are using a variety of methods to stack three or more active devices in a package.

This trend is evident among designers of integrated-circuit packages like Tessera Inc. (San Jose, Calif.), assembly and test companies like Amkor Technology Inc. (Chandler, Ariz.) and such semiconductor manufacturers as Mitsubishi and Fujitsu. The intent is to develop new packaging technologies that will benefit a variety of next-generation systems that include cell phones and other handheld devices.

Earlier this year, for example, Amkor concluded a multilevel technology-exchange agreement with Philips Semiconductors (Sunnyvale, Calif.). The pact covers intellectual property, process knowledge and patented or patent-pending technology. No products have resulted from the agreement as yet, but Amkor's "3-D," or stacked-packaging, lineup includes dice that are stacked three or more high, dice of the same size and different sizes, and side-by-side stacks.

Three-dimensional assembly allows the mixing of interconnect technologies within a package; for example, die-to-die or die-to-substrate, using wire-bond or flip-chip designs, according to Lee Smith, who is director of new-product development at Amkor.

Tessera Inc. (San Jose), initial developer of the microBGA (micro ball-grid array) package, is collaborating with Intel Corp. (Santa Clara, Calif.) on chip packaging for next-generation wireless and portable products. The effort is focusing on a chip-scale package (CSP) less than 1 mm high that contains three vertically mounted dice. In contrast, stacked-chip packages based on wire-bonded assembly technology and containing just two chips are approximately 1.4 mm high.

John Riley, Tessera's vice president of wireless business, said the Tessera-Intel package is intended to save cost, weight and board space. Tessera's stacked-die technology is designed to compensate for the different rates of thermal expansion and contraction between the silicon and circuit board, and to relieve mechanical stress. The package design requires no special materials, tools or processes other than a folding step.

"Folding stacked chips is simpler than wire-bonding assemblies," Riley said. "With wire-bonded multiple stacked chips, packages pass through wire-bonding tools multiple times. An additional step places a pad between chips to separate the dice, and clearance is needed for the wires that are bonded to the dice pads. It is a multistep manufacturing process with higher costs and taller packages that cannot be shrunk and still keep stress inside the package to a minimum to meet shock and vibration requirements."

Riley said stacked packaging employs both system-in-package and multichip-packaging concepts. In the Intel package, devices are mounted on a flexible substrate that is folded like a piece of paper. The resulting package is smaller, in both footprint and height, than a single thin small-outline package .

"Our vision for this technology is to leverage silicon integration and packaging integration to make possible an entire cellular phone in a single stacked-chip package. That would be necessary for a wristwatch phone or for other future wireless applications," said Riley. As important as size, he said, is "giving equipment makers the ability to combine more features inside their products."

Mitsubishi declined to say whether a partner was involved in developing a new memory device that contains four stacked chips in a micro multichip package. Recently announced in Japan for cell phone applications, it provides 96 Mbits of flash and 16 Mbits of SRAM using two chips of each type.

New cellular functions such as e-mail and Internet access call for larger storage capacities without a corresponding increase in package size or height, according to Narayan Purohit, vice president of the Memory Division in Mitsubishi Electric & Electronics USA Inc.'s Electronic Device Group (Sunnyvale). "Memory densities are increasing every six to nine months," he said. "It's hard to come up with a monolithic solution."

The most important factors in multichip packaging are selection of materials, placement accuracy and loop control during wire bonding, said Shin Nakao, packaging-technology manager for Mitsubishi Electric's Design Engineering Center-West. Nakao said Mitsubishi's packaging technology can be used in areas other than memory chips, but declined to reveal details.

Fujitsu Microelectronics Inc. (San Jose) is "doing a lot of chip stacking," including three as well as two dice, both for inhouse use and for sale to third parties, according to Alex Papalexis, Fujitsu's business development manager for advanced packaging technologies. "In some such devices, the dice are stacked vertically, but in others, a partial chip-scale design is used in which two dice are placed on one side of a substrate and a third is connected underneath.

"Most stacked-die packages are just for memory, or memory plus logic," he said, "but we are seeing requirements for multiple types of technology; for example, in optical networking, where gallium arsenide and indium phosphide might be combined."

Papalexis noted that some technologies cannot be combined on the same chip cost-effectively, so multiple dice-and not only memory-will need to be packaged together. "For the next three to five years, we'll see a lot of stacked-chip devices-until we can find a material that can accommodate all technologies, and even then there will be some features that are so rich they can't fit in a small area on a chip," he said.

Joint Electronic Device Engineering Council standards exist for combining two chips, but there are no specific standards for combining three or more, said Amkor's Smith, so companies are jockeying for the best position for their respective technologies.

But chip stacking is not only for cell phones and other portables. Irvine Sensors Corp. (Costa Mesa, Calif.) employs its NeoStacking scheme in multichip serial superconductor memory modules for future signal-processing needs.

"Serial superconductor memory is the only memory technology known that provides the speed of access and the data transfer rates necessary to match the future requirements of ultrafast processors for focal-plane-array signal processing and high-density, ultrafast telecommunications switches," Volkan H. Ozguz, Irvine Sensors' manager of 3D Silicon R&D, said. "Large-capacity superconductor memories will be needed to realize the full speed benefits of superconductor processing." Irvine's technology is being used to stack the superconductor memory chips in modules less than one inch square.

Kentron Technologies Inc. (Wilmington, Mass.) takes a different approach to high-density memory components. Its foldable electronic memory module assembly (Femma), which Kentron is licensing to memory module makers, connects one small printed-circuit board to another with a flex circuit. The boards contain off-the-shelf DRAM memory chips and standard thin-shrink small-outline packaging (TSS-OP), which, according to applications manager Badawi Dweik, have the advantages of cost and flexibility. "Stacked chips can only be used for high-density applications," he said.

Also, stacking creates the potential for thermal problems if a device's surface area is insufficient for heat dissipation. Dweik said Kentron is working now to standardize Femma packaging. "The next generation of memory will use BGA packaging instead of TSSOP, and BGAs don't stack, so Femma will be a good fit," he said.

BGAs are being used to stack chips at SyChip Inc. (Warren, N.J.), which was formed last year by Lucent Technologies. SyChip uses BGA balls to connect two 13 x 15 x 3.75-mm pc boards in a global-positioning satellite receiver module for wireless Internet appliances.

SyChip leverages "microsystem integration technology" developed at Bell Laboratories, product marketing manager Navi Miglani said, and working with circuitry and processes that are too costly and/or difficult to integrate on a single chip. He said the stacked design is enabling parts approximately 70 percent smaller than conventional components.

Solder-ball signals
The receiver module employs a stacked architecture to integrate baseband, RF circuitry-including passive components-and 8 Mbits of flash memory. The device needs only a real-time clock and an antenna to function, and the antenna signal is routed through one of the package's solder balls.

Most stacked-chip applications may be similarly vertical. "We're early in the three-stack curve," said Jody Noto, IC product marketing manager at Sharp Microelectronics of the Americas (Camas, Wash.). "We have the technology, but the market needs for three-stack devices are very diverse, and there's not just one that we could sell to everyone." Stacked-die technology may represent a cost saving, Noto added, but equally or more important are board space savings, more efficient routing and faster time-to-market.

COMPANY CONTACTS

Amkor Technology Inc.
(480) 821-5000
www.amkor.com
EETInfo No. 613

Fujitsu Microelectronics Inc.
(408) 922-9000 or (800) 866-8608
www.fujitsumicro.com
EETInfo No. 614

Intel Corp.
(408) 765-8080
www.developer.intel.com
EETInfo No. 615

Irvine Sensors Corp.
(714) 549-8211
www.irvine-sensors.com
EETInfo No. 616

Kentron Technologies
(978) 988-9100 or (877) 988-9100
www.kentrontech.com
EETInfo No. 617

Mitsubishi Electric & Electronics USA Inc., Electronic Device Group
(408) 730-5900
www.mitsubishichips.com
EETInfo No. 618

Philips Semiconductors
(800) 234 7381
www.semiconductors.philips.com
EETInfo No. 619

Sharp Microelectronics of the Americas Inc.
(800) 642-0261
www.sharpsma.com
EETInfo No. 620

SyChip Inc.
(908) 941-1111
www.sychip.com
EETInfo No. 621

Tessera Technologies Inc.
(408) 894-0700
www.tessera.com
EETInfo No. 622