The natural evolution of hardware as we now know it goes from board to single chip to system-on-chip. That is happening in today's networking design cycle and has revealed a unique design challenge classified as inductance.

We are familiar with the design obstacles associated with deep-submicron circuits like crosstalk, metal migration and the like. What often isn't modeled are the effects associated with very high-frequency circuits (500 MHz+ for digital, 1 GHz+ for analog), which represent a big chunk of design activity on the horizon. Bluetooth, for example, is 2.5 GHz in the wireless space, while OC-192-running at wire speeds of 10 Gbits/second-operates at a 10-GHz frequency. And it only gets worse, as designs topping 40 GHz (OC-768) go mainstream in a few short years.

At these levels the "skin effect" comes into play, where the resistance of wire increases with the frequency. As the frequency increases, the magnetic field near the center of the wire increases the local reactance. The charge carriers subsequently move toward the edge of the wire, decreasing the usable area and increasing the apparent resistance.

With RF- and GHz-speed, full-custom high-speed digital designs, parasitic resistances, inductances and capacitances from interconnect play a significant role in determining performance. Designers increasingly find that their schematic simulations do not match well with measured silicon. Problems such as lower-than-expected gain on amplifiers, impedance mismatches and timing skew can lead to chips that do not meet specifications or even outright failures. This has significant time-to-market and competitive implications. As feature sizes decrease and frequencies increase, interconnect parasitics will dominate even more, and the lack of accurate 3-D interconnect models available for use during design will result in even more problems.

A traditional full-custom design flow begins with designers verifying circuit functionality and performance in their main schematic simulations before moving on to the physical layout of the design.

Once layout is accomplished, attempts will be made to account for the parasitic effects of the interconnect on the physical design. Popular methods range from utilizing a less-accurate 1-D equation-based interconnect extraction tool to rough, hand-calculated estimates. Many designers simply rely on years of RF design experience to make intuitive estimates. It is also common for only lumped capacitance to be modeled, mainly for ease of calculation or due to limitations with the 1-D extraction tool.

Although these methods may have proved adequate in the past, they are increasingly problematic as silicon processes evolve and operating frequencies rise.

Once these parasitics are estimated, they are normally back-annotated to the schematic for re-simulation, to see how they will affect design performance. If problems are found, fixes are made to the schematic and layout. This main design phase loop is repeated until the designer is confident that the design will meet all specifications.

Unfortunately, the inherent inaccuracies in the interconnect parasitic estimates introduce significant error and design risk. For designs above 2 GHz, distributed resistance, inductance and capacitance must be modeled accurately in order to get a true picture of how the design will perform in silicon.

Full-custom design
In addition, for high-speed full-custom digital designs, accurate characterization of signal delay can only be achieved if the frequency-dependent skin effect on inductance and resistance is modeled correctly. Once the main simulations for the design phase have been completed, other analyses (e.g., noise analysis, substrate coupling) can then be performed before tapeout of the design.

Alternatively, a design flow that fully accounts for the parasitic effects of interconnect on design performance requires a fully distributed 3-D resistance, inductance and capacitance modeling of the interconnect, replacing the previous 1-D lumped capacitance modeling.

With this in place, the parasitic resimulation now becomes truly useful. The main design simulations and resimulations that take place in this design phase loop finally have accurate 3-D RLC parasitic models to use. Designers can now complete the design phase with accurate simulations. This will help eliminate problems at the silicon level.

A new class of EDA tools is now available to model and extract these inductance parasitics, and the tools have been successful in delivering greatly improved quality of results and time-to-market for these sophisticated, high-frequency chips.

One such product from Sequence, Columbus-RF, is being used by more than 20 customers worldwide. In addition to offering integrated 3-D RLC interconnect extraction specifically tailored for RF, analog and custom high-speed digital ICs, it is tightly integrated with the Cadence Analog Artist/Diva design environment. Tool interoperability is a must whenever a new addition to the "standard" flow comes into vogue.

Accurate analysis and correction of inductance is critical in high-frequency circuits. To be successful, a tool needs to predict the characteristics of RF and high-frequency analog circuits, accounting for gain and phase errors and oscillation, as well as parasitic relics of induction.

With accurate modeling, the necessity of overdesign and guard banding is eliminated, saving silicon real estate, reducing power and simplifying designs.