Changes in such areas as interrupt handling, packet processing, memory management and coprocessor interfacing should allow the MIPS architecture to better support embedded, real-time and networking applications, and put some distance between MIPS and rival ARM Ltd., according to David Courtright, director of product strategy at MIPS (Mountain View, Calif.).

The enhanced MIPS32/MIPS64 architecture will remain backward compatible and will be able to run legacy code. Similarly, existing third-party tools and operating systems will continue to function on the enhanced architecture but are expected to be upgraded over time to make use of the enhancements.

However, the actual improvements customers see will vary with implementation details and the applications software running on future MIPS processor core implementations, the company said.

Existing MIPS cores available for license, such as the 4K family, will receive the enhancements over time, the company said. The first core design based on the enhancements is due to appear in the second quarter of 2002.

Improvement details

As part of the enhanced architecture, MIPS is providing the framework for up to 16 general purpose register sets (GPRs). The current architecture supports one bank of 32 registers, so values in the register set must be stored away to memory if processing is interrupted. By allowing up to 15 shadow sets of registers, the need to save and restore GPRs when servicing an exception or interrupt is eliminated, the company said.

Similarly the original MIPS architecture supports a flat six-way interrupt that invokes a lengthy software interrupt handling routine. MIPS is now introducing a 16-way vectored interrupt structure and specifying an off-core method for supporting secondary interrupt handling.

Vectored interrupts minimize the processing required to determine the interrupt cause prior to interrupt handling. Vectored interrupts can save up to 20 cycles, significantly decreasing interrupt latency and increasing a processor's capability to manage millions of interrupts per second.

"Embedded applications are particularly interrupt driven," said Courtright. "Microcontrollers have traditionally had very strong interrupt handling. Now people are using microprocessors to replace direct hardware functions or to migrate from 8- and 16-bit microcontrollers."

To improve packet processing, something for which MIPS cores are used widely, the company is adding single-cycle instructions for bit and byte swapping and manipulation.

In the area of memory management MIPS is changing its base architecture to support a wider range of virtual memory page sizes. This currently extends from 4 kbytes at the low end and ascending by factors of four to 16 Mbytes. "We are adding 1-kbyte and 2-kbyte small pages and 64-Mbyte and 256-Mbyte large pages," said Courtright. "The large pages are useful for routers building routing tables and servers with large databases. It lets the TLB [translation lookaside buffer] be shorter and reduces the penalty from a TLB miss."

Finally, MIPS is adding specific instructions to improve manipulation of 32-bit and 64-bit data between MIPS cores and coprocessor cores.

Although performance improvements may depend on implementation and applications, Courtright cited the example of IPv6 (Internet Protocol version 6) packet forwarding that could use some of the added features of the architecture to perform its basic function in 13 instructions rather than 20, thereby running 54 percent faster.

Reacting to the contention that MIPS' additions mark a belated attempt to turn a computer-oriented processor architecture into one supporting embedded systems, Courtright said: "These things have existed in other computer architectures, but as more and more applications come into our space we are having to evolve the architecture.

"It's a combination of enhancements driven by applications and extending our capability beyond what is required," he said. "For example, the interrupt performance is moving from tens of microseconds to something on the order of hundreds of nanoseconds — more than an order of magnitude improvement in the potential interrupt latency."

Courtright also argued that MIPS has established a significant lead over its main rival in licensable processor cores, ARM Ltd. (Cambridge, England).

"This [new set of features] is much better than what ARM has, at least in terms what we know of ARMv5," said Courtright. "The interrupt performance should be much better; the memory management support is much wider. And ARM does not have 64-bit CPUs."

John Rayfield, director of R&D at ARM, is due to present details of version 6 of the ARM instruction set architecture at the Microprocessor Forum on Wednesday Oct. 17, just before MIPS' director of architecture Michael Uhler makes his presentation on the MIPS32/MIPS64 enhancements.

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