NAPA, Calif. — Implementation of the new Verilog-2001 hardware description language became practical with the IEEE's release Wednesday (Oct. 17) of documentation that describes the standard, officially known as IEEE 1364-2001. Meanwhile, some EDA vendors are quietly moving ahead and adding support for Verilog-2001 constructs.
Although the IEEE approved Verilog-2001 in March, until now only a handful of people have had access to working versions of the documentation, said Dennis Brophy, chairman of the Accellera standards organization. "Now we have the authenticated version from the IEEE that's ready for the rest of the industry to use," he said.
Compared to previous versions of the language, Verilog-2001 promises to let designers work at a higher level of abstraction, and to achieve more timing accuracy for deep-submicron ICs. It also promises better simulation control and improved tool interoperability through an enhanced programming language interface (PLI).
While chip designers have yet to get up to speed on Verilog-2001, a few EDA vendors who have been involved in the standard's development are already moving ahead. For example, Cadence Design Systems Inc. has added some Verilog-2001 constructs to its PKS synthesis and NC-Sim simulation tools and will add more based on user demand, a spokesman said.
Co-Design Automation Inc. worked in parallel with the Verilog-2001 effort, and its Systemsim simulator supports Verilog-2001, said Simon Davidmann, chief executive officer of Co-Design. Superlog's additional language capabilities are "built on the Verilog-2001 base," he said. Mentor Graphics Corp. has implemented "substantial parts" of Verilog-2001 into ModelSim, said Anne Sanquini, vice president of Mentor's HDL design division.
Higher models, faster code
Behavioral extensions in Verilog-2001, Brophy said, are aimed at letting users create higher-level models and write code faster. He said that the addition of "configuration" blocks will allow for better design management and that "generate" statements, a concept borrowed from VHDL, will help prevent repetitious coding. Other new language features include multidimensional arrays, improved file I/O and re-entrant tasks.
To support more accurate ASIC and FPGA timing, Verilog-2001 adds support for on-detect pulse error propagation, negative pulse detection, new timing constraint checks, negative timing constraints and enhanced Standard Delay Format (SDF) support. The Verilog Charge Dump (VCD) file format has been extended beyond four states to support more detail on net strength and port changes.
New features added to the Verilog programming interface (VPI), which is part of the PLI, provide improved control over simulation and debugging, Brophy said. He also noted that new VPI functions allow for better integration of C language models.
The PDF version of the IEEE standard 1364-2001 is available now, with the print version coming in late October. These can be ordered at www.ieee.org. Meanwhile, consultant Stuart Sutherland has a Verilog-2001 FAQ at www.verilog-2001.com. An updated Verilog 2001 tutorial by Sutherland is available at www.EEdesign.com.
