Logic analyzers can be connected to signals at the interfaces between chips, and sometimes they can be linked to on-chip debugging interfaces to view data flow inside FPGAs and network processors. The other main value of a logic analyzer is the ability to correlate data from multiple interfaces onto a single time domain. This allows the designer to track the flow of data through a system, rather than debugging from a single bus. Data from data path buses, memory interfaces and microprocessor buses can all be viewed in a single time domain.

All those capabilities marry well to the requirements of debugging router designs. Routers can be broken into three main subsystems: packet-forwarding cards, switch fabric and system control cards. Packet-forwarding cards perform data transmit and receive operations, a portion of the routing-table lookup and scheduling. The switch fabric subsystem contains a high-speed crosspoint switch. System controllers perform system-management and monitoring operations along with the routing decisions that aren't handled locally on the packet-forwarding cards. The system board typically communicates with the line cards through the control bus, often a CompactPCI interface.

The interface between the physical-layer and media-access control (MAC) devices and the traffic-management devices are largely standardized. That said, there are different options based on chip integration and vendor selection. For example, in Gigabit Ethernet applications, you may have a serializer-deserializer (Serdes) that passes data across a 10-bit interface straight into a network processor, which performs 8b/10b encoding/decoding and MAC functions. Or a single, integrated chip may include the Serdes and 8b/10b functions, outputting data on a Gigabit Media Independent Interface bus. At higher speeds, functions are often broken up into separate chips, due to different chip process requirements, economics or a need for compatibility with existing parts.

Interfaces between traffic-manager chips and data storage are typically standard, such as SRAM and double-data-rate SDRAM. Switch fabric interfaces have traditionally been proprietary, but efforts are under way (including that by the Common Switch Interface, or CSIX, Consortium) to create a standard interface between line cards and switch fabrics.

Some next-generation I/O buses have changed the rules of logic analysis. Traditionally, a revision of a bus standard would quadruple its aggregate bandwidth by doubling both the bus width and the clock speed. For example, to go from OC-12 (622 Mbits/second) to OC-48 (2.5 Gbits/s), the POS-PHY Level 3 bus standard doubled the bus width and clock speed over its predecessor, Level 2. However, OC-192 system designers realized that routing a 64-bit-wide bus with a 200-MHz clock would come with board-routing, power-consumption and crosstalk problems.

Low-voltage differential signaling has been shown to be effective at much higher clock rates. Using LVDS at over 800 Mbits/s, 16 channels (32 wire pairs) can provide the same aggregate bandwidth as 64 channels running at 200 MHz, with less power consumed and less crosstalk between channels. These buses typically have a clock speed of one-half the bit rate. For example, a bus with 800 Mbits/s per channel would use a 400-MHz clock and transfer data on both rising and falling edges. Example implementations include POS-PHY Level 4 (also known as SPI-4), RapidIO and HyperTransport.

To capture data flow on these buses requires a new type of logic analyzer. Agilent Technologies has developed the 16760A module to capture state-mode data at up to 1.25 Gbits/s (625-MHz clock, using both edges). A special front end and high-sensitivity probing allow for passive probing with minimal interference. With a memory depth of 64 Mbits on 34 channels, up to 2.6 million 100-byte frames can be captured in real-time.

At high speed and low voltage, traditional logic analyzer probes would interfere with the successful transmission of signals, which defeats the purpose of testing. Even small amounts of additional metal on a trace add capacitance, which reduces bandwidth. For that reason, a special low-capacitance surface-mount connector is the preferred way to probe LVDS signals up to 1.25 Gbits/s. The 16760A LVDS logic analyzer uses an innovative probing system with only 1.5 picofarads of probe tip capacitance, including the connector. The connector is optimized especially for logic analysis measurements. In this probing solution, ground pins located between every pair of signal pins provide excellent channel-to-channel isolation at high speeds.

It's useful to break out the equivalent load added to the target device by the new differential probe. The 1.5-pF capacitance is added by the surface-mount mating connector, and the remaining resistors and capacitor come from the probe's termination network and pod cable.

What isn't included in this equivalent load is the effect of the added stubs that lead from the signal trace to the probe connector. The stub, acting as a transmission line, can degrade the bandwidth of the target signal. The trace can be isolated from the transmission-line capacitance by placing a series resistor as close as possible to the signal trace. This resistor and the transmission line to the probe tip degrade the bandwidth of the signal arriving at the probe tip, so resistor values and stub lengths must be chosen carefully to avoid degrading the signal arriving at the probe. Ultimately there are two requirements to meet in designing in the probing: adequate isolation of the target trace from the probing system and minimum eye opening at the probe tip, which is 500 ps wide and 200 mV high.

At high speed, capturing data within very small data-valid windows becomes key. The sampling position relative to the clock edge must be fine-tuned individually for each channel. The 16760A allows for adjustment of the setup and hold position in increments of 10 ps, and sampling on a minimum data-valid time of 500 ps. Agilent has developed a new method for automatically computing the optimal sampling position on all channels. This tool, called Eye Finder, uses the logic analyzer's comparators and sampling hardware to find stable regions on each channel. The software automatically positions the analyzer's sampling position in the center of the stable region. While not a replacement for a high-performance oscilloscope, Eye Finder allows for a quick perspective of signal integrity on many channels simultaneously, in addition to easier configuration of the logic analyzer.

Logic analyzers have many features for providing a high-level, decoded perspective of data flow on standard data path buses. If you can connect your logic analyzer to a standard bus you may be able to see very high-level analysis of data traffic. The decoded view can help solve problems in chips that do not comply with bus specs; when a bus does not comply, the decode display will fail. Examples of such failures include preambles or carrier-extension words of invalid length; invalid 10-bit codes; sequencing errors (such as Start of Packet found between the Start of Packet and End of Packet); and data corruption.

Decoding data from a single bus is useful, but the true power of a logic analyzer lies in the ability to bring data from multiple buses together on a single time scale. Take, for example, a packet traveling through a Gigabit Ethernet router. That packet then enters a programmable network processor, which stores it in DDR buffer memory while deciding where to send it and when to schedule it before reading it back out and sending it on its way. The logic analyzer's time correlation makes it possible to measure latencies between subsystems and components, in addition to providing basic visibility. This type of measurement can be used to solve problems such as excessive latency in packet forwarding and dropped or lost packets.

Often the symptom of a design problem can be seen in another test instrument, like a protocol analyzer or traffic generator and analyzer. Because such instruments can see packet traffic only on the external interfaces of the system, they cannot pinpoint the source of the problem on their own. In such a case, an external trigger signal can be passed from the other instrument to the logic analyzer, to capture data and signal flow during the period leading up to the failure. Using the deep acquisition memory of the logic analyzer, a designer can then look back in time before the failure to track the system's behavior. This technique can be used to solve such problems as incorrect packet forwarding or insufficient system throughput.

The logic analyzer is a key tool in problem solving during the turn-on of new router prototypes. It provides high-level visibility of data flow between chips (and sometimes even inside them). Concurrent visibility across multiple domains makes it possible to pinpoint the source of failures and performance issues. As technology evolves into ever-increasing speeds and decreasing voltages, logic analyzer probing and acquisition technology is keeping pace, and will continue to be there when designers need it in the future.