At this week's Network Processors Conference in San Jose, Calif., at least three companies — Applied Micro Circuits Corp., Silicon Access Networks Ltd. and Entridia Corp. — will detail their OC-192 architectures. All expect to sample their parts by January.

But with the network processor market still in its infancy and with the communications market in a general malaise, it's unclear how strong the call will be for 10-Gbit/s processors. Motorola Inc. is revealing its plans for 10-Gbit/s chips this week, but the company's real focus remains on OC-48 (2.5 Gbits/s). IBM Corp. likewise believes the 10-Gbit/s NPU market has not yet arrived.

Separately, traffic management is becoming a strong focus among network processor vendors as it becomes clear that high-end NPUs will require coprocessors. Motorola officials will emphasize a new traffic-management coprocessor that will accompany the OC-48 and OC-192 network processors. And chip maker EZchip Technologies will announce details of its off-chip traffic manager as well.

Future focus

Increased competition has put pressure on network processor vendors to announce their OC-192 plans even though most NPU sales continue to be at the OC-48 level.

"There's no question OC-48 is going to be a much bigger seller than 10-Gbit/s parts for the next couple of years," said Linley Gwennap, principal analyst of The Linley Group (Mountain View, Calif.) and chairman of the Network Processors Conference.

For that reason, Motorola and IBM aren't bothering yet with formal OC-192 announcements.

OC-48 is "going to be a great market for many years," said Steve Longoria, director of marketing strategy for IBM's NPU efforts.

"Not that we're not going to be in the 10-Gbit/s space — we are — but I'm seeing a lot of chest pounding and vaporware."

Bob Gohn, vice president of marketing for Motorola's C-Port organization, agreed that OC-192 NPU vendors are "shooting ahead of the duck," adding that the processors being proposed might not hit the level of services that will be required at 10 Gbits/s.

Gwennap agreed that 10-Gbit/s NPUs could be considered "vanity devices" but noted that they might help companies stay in the spotlight while the 10-Gbit/s market germinates. "By the time [IBM and Motorola] get out there, will they be able to wedge themselves into designs?" he said.

Finally, Gwennap noted that a 10-Gbit/s NPU doesn't have to connect to 10-Gbit/s lines. Chip vendors have talked about using the processors to handle four lines of OC-48 or 10 lines of Gigabit Ethernet, for example. They could also be used to add more complex processing of slower-speed transmissions. "People have been complaining a lot about not having enough cycles on these OC-48 parts," Gwennap said.

Drawing a crowd

Peer pressure may have the final say, however, since network processor vendors including Vitesse Semiconductor Corp., Intel Corp. and IP Semiconductors A/S have announced their 10-Gbit/s architectures already. "Everybody and his brother is talking about 10 Gbits/s, because everybody would be ashamed if they didn't have a story," said Robin Melnick, director of marketing for AMCC.

It's possible that AMCC (Sunnyvale, Calif.) will have the first of the 10-Gbit/s NPUs to ship, as sampling is expected by the end of the year. But with at least two other companies planning January shipments, the timing won't be much of an advantage, Melnick said.

AMCC will announce details of the nP7510, its 10-Gbit/s NPU, at the Network Processor Conference this week. The company aimed to make the nP7510 as similar as possible to its OC-48 NPUs, avoiding the "radical designs" of startups, Melnick said. The chip uses the same processor cores as its predecessor but needs six of them compared with the two cores used at OC-48. AMCC's programming environment will treat the six cores as a single processor, just as it did in prior releases.

The first release of the nP7510 will be a unidirectional part. Roughly nine months later, AMCC plans to release a bidirectional version based on 0.13-micron process technology, Melnick said.

Also chiming in at 10 Gbits/s is Entridia (Irvine, Calif.), which takes a hardwired approach to network processing. Entridia is introducing Rhapsody, a 10-Gbit/s packet processor, at the conference. Among the key features of the chip is its packet modification engine, a "massive" arithmetic logic unit that can do "pretty much anything to the packet header you want," said Omar Hassen, Entridia's director of strategic marketing.

Due to sample in January, the chip targets both Sonet OC-192 and 10-Gigabit Ethernet. "We internally couldn't come up with a solid vote as to which would win," Hassen said.

Silicon Access Networks will announce details of its flagship iPP packet processor next week. The iPP actually has a 20-Gbit/s throughput and is targeted mainly at aggregated Gigabit Ethernet feeds. "There're a lot more Gigabit Ethernet ports in the world than there are OC-192 ports," said Mitch Kahn, Silicon Access vice president of marketing.

Due for first shipments in January, the iPP consists of 32 multithreaded processors grouped into four clusters called iAtoms. On-chip buffers measure 1,024 bits wide to handle the data throughputs required beyond 10 Gbits/s.

The C-Port division of Motorola will discuss its upcoming C-10 NPU for 10-Gbit/s lines, but the company is not announcing the chip just yet, choosing instead to emphasize more complex processing at OC-48 rather than push to OC-192, Gohn said. To that end, Motorola is announcing an external traffic manager intended to boost services.

Traffic management

Traffic management — the prioritizing of the data flows being fed to the switch fabric — is proving to be among the most difficult of the network-processing steps, prompting many companies to use separate traffic-manager chips at the high end. Traffic management is "the last place of the last places where they want to use merchant silicon," Silicon Access' Kahn said.

In many cases, the amount of memory required for these queues is what drives high-end traffic management to be handled outside the NPU. "The guys doing it in software [on a programmable NPU] are handling only a handful of queues," Gwennap said.

Motorola this week will announce the Q-5 traffic-management chip and the C-5e, a version of the C-5 modified to interface with the Q-5.

The Q-5 is a full-duplex chip that can handle up to 256,000 separate queues — extra queues being a critical means of separating individual users' traffic into different levels of priority. The Q-5 handles only control information for traffic management; the buffers for the actual queues are kept off-chip in double-data-rate DRAM.

Separately, Motorola is announcing the M-5 channel adapter, which can be used in conjunction with the C-5e to groom OC-48 traffic down to the STS-1 (51-Mbit/s) level. The C-5e, Q-5 and M-5 are all due to begin sampling in the second quarter of 2002.

EZchip discussed its QX-1 traffic manager at Networld+Interop, but is revealing details for the first time this week. The device is an adjunct to the ingress and/or egress paths of the company's NP-1 network processor.

EZchip developed the NP-1 to be a self-contained single chip loaded with embedded memory. However, that 4 Mbytes of memory isn't sufficient for the tens or hundreds of thousands of queues demanded by more-complicated applications.

Each QX-1 can add a buffer of 48 to 768 Mbytes, and one can be put on both the ingress and egress sides of the NP-1. The chip is also useful to segment the OC-192 traffic that passes through the NP-1; flows in the QX-1 can be channelized down to the OC-12 (622-Mbit/s) level.

In a similar vein, Entridia plans to introduce a queue-management chip for 10-Gbit/s traffic, Hassen said.