The technology builds on Tensilica's existing compiler, which generates customized processor engines based on user-defined instruction sets. The augmented version will take this to the next level of abstraction, taking in C-code and automatically spinning the best instruction set and hardware implementation according to performance and cost guidelines set by the user.

"In the past you had to select and describe what you want. The next step is to have the compiler itself evaluate all the possible instructions sets. The key idea is that you can make the processor fit the problem," Rowen said.

When the technology is ready for deployment, Rowen predicts, users will input C or C++ code that would otherwise be used to program a fixed-function microprocessor or DSP.

"It knows the cost of registers and memory and can figure out a wide range of potential architectures based on performance and silicon costs. We're automatically creating a much larger range of options so that you can explore thousands and thousands of different architectures," he said.

At the recent Microprocessor Forum here, Rowen explained how the compiler technology can take less than a minute to generate gates for a Fast Fourier Transform (FFT) algorithm. During that time it evaluated almost 1,000 configurations before choosing a final architecture, Rowen said.

The new technology builds on Tensilica's existing compiler, which contains the basic algorithms for building vectors, software pipelines and operation packing. After weighing cost and performance trade-offs for all the possible iterations, it selects the final architecture and generates the code, including the processor-generator that is part of Tensilica's current offering, Rowen said.

The enhancements, still in the early stages, need more tuning and verification, Rowen said, before the compiler is ready for the market. He did not speculate on when the technology will be introduced.

But if the technology preview is any indication of what's coming, it's only a matter of time before processors are considered just another building block for system-on-chip design, just as transistors are for today's devices. Moreover, system architects won't be beholden to a select group of processor designers, Rowen said.

"You can be at least as competent as those elite guys," he said. "You'll see an explosion of designers that can work in that zone."