Recently approved as a Jedec standard, scalable low-voltage signaling (SLVS) has yet to gain a groundswell of support needed to kickstart broad development. Backers are initially targeting telecom systems and network processors.

Philips Semiconductors, which spearheaded the definition of SLVS, plans to support the scheme in its upcoming 0.13-micron process technology as a chip I/O and serial backplane interface. Co-developer Cypress Semiconductor Corp. has created a high-speed version, LiteLink, that it is proposing as a chip interface standard to the Network Processor Forum and the IEEE 802.17 committee on metropolitan optical rings.

SLVS promises to enable signaling at rates from 1.25 to 3.125 Gbits/second over distances of less than 30 centimeters while drawing as little as 6.4 milliwatts, potentially cutting in half power consumption of the current low-voltage differential signaling technology. Cypress has developed what it calls a pseudodifferential coding scheme that aggregates 11 SLVS lines into a 10-Gbit interconnect that it has proposed as a standard interface for network processors and resilient packet ring media access controllers.

Engineers familiar with the technology praise its basic merits, but none are ready to commit development resources to it until the technology receives broader public blessings from standards groups and communications OEMs. Priming the pump, Philips said it will roll out test chips for SLVS over the next six months.

"The technology appears to be interesting and promising, but we're just in an evaluation mode at this point," said Douglas Stout, engineering team leader for ASICs at IBM Corp. "We haven't made a decision to offer SLVS in our ASIC products. We'd like to see more customer demand first.".

The LiteLink version of the technology is an alternative to more-complex serializer/deserializer (serdes) interfaces being debated for next-generation network processors and the ternary CAMs, SRAMs and coprocessors that connect to them, said Michael Miller, a systems architect at SRAM and network silicon maker Integrated Device Technology Inc. (Santa Clara, Calif.).

The serdes approach requires "the equivalent of digital phased-lock loops which means a lot of uphill climbing," Miller said. By contrast, "LiteLink does look feasible, but we haven't started any development work on it yet. I'd like to see more interest from our customers in that area and support as a standard from groups like the Network Processor Forum."

The LiteLink proposal,also known as balanced-code transceiver logic, is one of five physical layer proposals received by the Network Processor Forum for the so-called Look Aside 2 (LA-2) interface it is defining. LA-2 would link network processors with a growing variety of communications coprocessors and memory devices. Other LA-2 proposals include HyperTransport, something called HiBus from Intel Corp. and variants of existing SPI4 and SPI5 interfaces. The forum will pick one of the proposals in April after evaluating them at meetings this month and in January.

Meanwhile Philips is trying to rally support for SLVS, and Cypress is pushing for its LiteLink variant especially among top communications OEMs including Alcatel, Cisco and Tellabs.

"As soon as the optical module makers adopt the SLVS interface we will see rapid use of it," said Mark McDonald, a senior systems architect at Philips Semiconductors. "There's no active development from OEMs at this point."

To get the ball rolling, Philips is developing a test chip using SLVS in its 0.18-micron technology this year. It plans a more-complex test chip in 0.12-micron technology using 8-24 serdes channels and SLVS I/Os running at 1.25, 2.5 and 3.125 Gbits/s by next April.

For its part, Cypress has drafted a specification for resilient packet rings using LiteLink as a MAC-to-client chip interface and submitted it to the IEEE 802.17 committee which is currently reviewing competing proposals from Cisco and Nortel.

"I think there's about a 50-50 chance of this staying as an active proposal for 802.17," said David James, a chief architect in Cypress' data communications division and developer of LiteLink. "I'm really trying to force the committee to develop a proposal that's more exactly defined."

Saving power and pins

SLVS was born as a clean-slate effort to design a signaling technology that breaks out of the limits of existing techniques such as low-voltage differential signaling. LVDS faces difficulties as core device voltages continue to drop in slow increments from 3.3 V to below 1 V.

To insulate itself from that stepwise voltage decline, SLVS uses a 0.8-V power supply, sends signals at voltages between zero and 0.4-V and terminates its signal to ground.

"We were seeing Jedec come out with 1.5-, 1.4- and 1.3-V standards, so one of our first design specs was to reference off-ground," said James.

"I don't like duck-walking under a descending ceiling," said D.C. Sessions, a senior engineer at Philips and chairman of the Jedec JC-16 group that defined SLVS. "Every new process technology has required us to re-architect our I/Os, and I/Os have now become the longest part of the design to deliver."

LVDS is also facing performance issues, Sessions said. "At 0.13-micron performance using LVDS will start to get worse," he added. "All of a sudden we are using older transistors to deal with the lower voltages and that means the device's performance goes down."

By switching to SLVS, designers will not have to sacrifice device performance for power and the technology should hold up through several process generations, said James, who also edited the LVDS spec. "I think SLVS will be good for five to six years," he said.

Radically lowering the power of I/O signaling will have a significant impact on overall power consumption for chips using SLVS. "Some chips today require 3 watts just to power the I/O," said Sessions. "That's starting to cause package problems. SLVS will bring that down to 0.5 W, which saves a lot of grief."

Ternary CAMs now run at 4 to 20 W. Adding 4 W for high-speed I/O would be unacceptable, said James.

The LiteLink proposal uses even less power than SLVS — about 2 mW — because it does not terminate power to ground. Instead it checks the average power of its signals creating a pseudodifferential scheme that does not require an interim 0.4-V power supply. But the technique takes a hit on performance, aiming at 1 Gbit/s per pin in its initial incarnation. "We figure there's an upgrade where you can double that," said James

The availability of Gbit/s signals in LiteLink and SLVS could also help reduce pin counts, easing both design of chips, which are becoming pad-limited, and pc boards, which are seeing crosstalk problems from a burgeoning number of fast traces. The LiteLink interface could be an extra help here because it offers a cascading capability so a network processor might have one LiteLink interface to a ternary CAM that would in turn use LiteLink to talk to an SRAM and then an encryption coprocessor.

The cascading feature could lighten the I/O load on net processors, many of which are already sprouting 1,000 to 1,500 pins, said James.

"The main applications for SLVS I am aware of right now are in the telecom space," said Sessions. "They want to move absolutely mind-boggling amounts of data between chips. One company working on network processors is looking at this for using 128 I/Os on a chip. We have seen several requests for proposals of that nature. They are our early adopters," Sessions said.

One downside of SLVS is that it requires use of power/voltage/ temperature (PVT) compensation techniques. That means using a reference pin attached to a reference resistor to monitor impedance so the device can adjust its performance levels as needed. The technique is already used in high-speed design, such as AGP 4x graphics interfaces on high-end PCs. But "a lot of logic designers are not used to doing that," said Sessions.