With these architectural improvements, the company hopes to convince designers of digital cameras, DVD players, PDAs and the like to use programmable logic instead of ASICs. Xilinx has created a Web portal on this topic at www.xilinx.com/esp that includes reference designs, tutorials, glossaries and discussion forums.

Spartan 2e is the main focus of Xilinx's drive into digital video. The I/O supports speeds of more than 300 MHz, fast enough to match the performance requirements of 19 I/Os. These include LVDS, BLVDS, LVPECL, AGP, HSTL, SSTL, 1394 and USB 2.0. The support for differential signaling at speeds of 400 Mbits/second can be used for compressing multiple RGB signals from a video source to a flat display panel.

Low-voltage differential signaling should also help designers overcome issues related to electromagnetic interference. "One area people don't spend a lot of time thinking about is EMI," said Robert Bielby, senior director of strategic-solutions marketing for Xilinx (San Jose, Calif.). "LVDS goes far in enabling lower shielding, lowering pc-board traces and getting through EMI approval."

The Spartan 2e is also said to have the muscle to handle a range of digital signal-processing functions like Viterbi decoding, Reed-Solomon and color-space conversion. These functions are enabled through the company's System Generator software interface, which links its FPGA tool bundle to the Matlab Simulink DSP tool.

Based on the Virtex E FPGA, the Spartan 2e contains 50,000 to 300,000 system gates, depending on the version, and can surpass 200-MHz speeds. Manufactured on 0.18-micron design rules, the family has a core voltage of 1.8 V and can tolerate 3-V I/O. A series resistor is required if 5-V I/O is used.

To reduce costs, the Spartan 2e has half the block RAM of the Virtex E. Xilinx divides its RAM into two categories: distributed RAM, which is closely coupled to the logic cells and used for things like distributed arithmetic in digital signal processing; and block RAM, which handles line and frame buffers.

The company said stripping away some of the RAM is a safe bet. "We're finding that even in Spartan 2, designers are not using all the block memory that's there," said Steve Sharp, senior manager of silicon solutions marketing.

In another cost-saving move, Xilinx introduced a lower-cost version of its 256-pin fine-pitch ball grid array package with two fewer substrate layers than before. The Spartan 2e is not pinout or bit-stream compatible with any other Xilinx FPGA family. Prices for the five members of the new family range from $13 to $35, and are expected to be half of that by late 2002, Xilinx said.