With the exception of the capacitor insulator film, all materials of the process are metal. It will build chips that can replace SRAM in communications and high-end server applications, the company said. First silicon is due in January and mass production will begin next summer. The technology performs radically better than NEC's 0.15-micron eDRAM process, said Shuji Kishi, project manager at NEC Corp.'s ULSI Device Development Division (Kanagawa, Japan).

In a paper presented Wednesday (Dec. 5) at Semicon Japan 2001, Kishi said the speed improvements come through several innovations.

At 0.331 micron², the 0.13-micron DRAM cell is smaller than the 0.422 micron² cell of NEC's prior-generation process, and contributes to a 10 percent reduction in block size that reduces resistance in the circuit's bit lines. NEC will settle for a slightly larger 0.35-micron²cell size when it moves the process to mass production, Kishi said.

"The cells are actually not all that small," he said. In fact, Toshiba Corp. has built a 0.19 micron² cell that it plans to use on its 100-nm eDRAM technology. "But we are concentrating on speed," Kishi said, "so we have to think of the right tradeoffs in other areas."

Speed hurdles

Embedded DRAM technology faces speed hurdles all around a circuit, with brakes applied by channel resistance, contact resistance at the capacitor node and bit line resistance. NEC said it has tackled these problems comprehensively.

Kishi said its adoption of co-salicide technology tremendously cut channel resistance by lowering the parasitic resistance in the cell transistor. Next, it stripped out the conventional polysilicon capacitor and adopted a tungsten buried capacitor contact that slashed resistance to one-thousandth the level of the previous-generation technology. Tungsten was also adopted for the bit lines themselves, a move that cut line resistance about 80 percent.

The full-metal DRAM technology has the added advantage of requiring only a 500°C thermal budget, Kishi said. The process was created by adding between six to nine additional masks for a 0.13-micron pure logic process, which features copper interconnects and a low-k dielectric.

NEC announced an alliance with Atmos Corp. earlier this year to push eDRAM into chips such as network processors and DSPs for use in products such ATM switches, routers and high-end servers. As part of the deal, Atmos (Pescadero, Calif.) will develop eDRAM macrocells and test chips.

Integrated device manufacturers (IDMs) in Japan, notably NEC and Toshiba, have struggled for years to find widespread applications for eDRAM, but customers have been unwilling to pay a premium for the technology's performance benefits. Other chip makers remain cautious about eDRAM's chance of moving past its niche status.

Taiwan Semiconductor Manufacturing Co.'s 0.18-micron embedded DRAM technology flopped in 1997 when the company found nobody was prepared to pay its higher prices, said Ken C. Chen, director of field technical support and marketing at subsidiary TSMC Japan K.K.

"TSMC believes that 1-T SRAM will continue to support the majority of needs for our customers and market demand in the foreseeable future," he said. "We are quite happy to see our Japanese partners and Japanese IDMs develop embedded DRAMs and forge their own businesses."

TSMC saw the adoption of embedded DRAM as problematical, Chen told EE Times. As with silicon-on-insulator technology, TSMC lacks the design libraries, intellectual property and know-how to crank out product, he said. The company remains unwilling to invest in such technologies until it has both comprehensive partnerships and evidence of a big enough market.

But Kishi said NEC is confident that the need for speed in high-end applications, particularly in communications, would create demand for eDRAM starting next year. NEC has already held talks with several high-profile chip makers who "were very interested" in the full-metal DRAM technology, though Kishi declined to name them.