That first impression would stand up well against Faggin's history. The Italian-born former Intel Corp. designer founded Zilog Inc. in 1974, co-founded Cygnet Technologies Inc. in 1982, and launched Synaptics Inc. in 1986, with Carver Mead. Faggin was chief executive officer and president of the San Jose, Calif., developer of custom user interface solutions from 1987 to 1998, and has been chairman of the board since 1999.

He is a recipient of many honors and awards, including the 1997 Kyoto Prize, and in 1996 he was inducted into the National Inventor's Hall of Fame.

But Faggin's career is indelibly stamped with one event: He was the designer who in 1970-71 implemented the Intel 4004, arguably the first commercial microprocessor chip.

In belated recognition of this 30th anniversary, EE Times spoke with Faggin recently about the design of what was then one of the most complex digital ICs in history. The 4004 was not only a progenitor of the modern microprocessor, but also gave birth to a chip design methodology.

EE Times: To get a feel for what the chip was like, maybe we should start with the process you were designing for.

Faggin: The process was important, because we were doing a really big chip — about 2,300 transistors — and some of the process innovations were critical to getting a usable die size.

First was the use of buried contacts — connecting the polysilicon directly, without the use of metal. This in effect freed the metal layer to act as interconnect, giving us a second interconnect layer that was critical for the component density we needed.

The second issue was the use of bootstrap loads. Bootstrap loads add a second load transistor and a capacitor, like so . . . (Faggin, characteristically, searches out a tablet and pen to illustrate his point). When the circuit switches, this capacitor carries the transient current and the output doesn't stop at the voltage-divider level between the switching and load transistors, it can go all the way to - 15 volts.

That makes possible some very useful circuit elements, like dynamic storage cells, that you can't do with static loads. But it requires this capacitor, here, and everybody thought you couldn't build the cap without an additional mask if you had a silicon-gate process. I discovered how to do it. Again, it was a density issue: If we'd had to use static storage cells, we could never have put everything on one die.

EET: So that was the famous 10-micron process. How did you go about designing the chip?

Faggin: The way we designed a chip back then was to do a 500-times real-size drawing on a big piece of paper with colored pencils. The pencil drawings were sent down for artists to trace and cut rubylith, which was photographed to make the masks. We worked directly on the drawing, so you had to visualize a block of logic as a layout.

EET: Close your eyes now and visualize the 4004 arithmetic logic unit. What do you see?

Faggin: I see a drawing of the ALU layout kind of superimposed on the schematic. We didn't do schematics as such for the 4004, we worked directly from the concept of what the block was supposed to do to a layout drawing.

(Faggin sketches a PMOS inverter — from memory. As he draws, his hands carefully enlarge the gate poly strip to leave clearance around the contact, as if they had learned the design rules themselves.)

EET: Working at that level of detail, how did you conceive and lay out an entire CPU?

Faggin: There had to be an address stack, a register file and an ALU. I decided that rather than trying to wire things point-to-point, I'd use a 4-bit bus that wrapped all the way around the chip.

The bus was going to be one big capacitor, so I'd just as well use it for storage. And that's what it is on the 4004 — a storage location that's accessible to all the blocks, and can hold data.

Then, with some idea of the size of each block, I worked out where to place each one so that the chip came out a rectangle with no big unused space. The control logic had to go in the center for two reasons. First, we had to keep the routing paths short for timing reasons. Second, with only two layers of interconnect, the only way that the control logic could connect to all the other blocks on the chip was if it were centrally located.

The I/O went on the outside, on the other side of the bus from the functional blocks. That way it also had bus access.

Implementing the control logic was a challenge. You couldn't just think of it as a functional block, because it reflected the sequence of events. I divided the control circuits up into stages: First, decode the state of the CPU, then re-encode the next state.

Then I would combine the state information with the gross timing information, in some cases saving the result in a storage node for a while. Then I'd gate that information with the clock to actually drive the functional blocks. So the control circuitry kind of flowed into place.

EET: How did you go about verification?

Faggin: The only simulation tool we had was Spice running on a time-share service. I used that to check some tricky interactions in the I/O pad design, but otherwise there was no simulation. Verification was by checking things over and over again. There wasn't any other designer working with me, so I had to check a lot of my own work.

We probably spent three or four weeks just checking rubyliths. You would go in in the morning and start checking a rubylith, and you'd just keep at it until your eyes were about the color of the ruby film. But little pieces of the film would sometimes get stuck somewhere else on the sheet. Or a piece you didn't intend to remove would come loose. Sometimes the rubylith would do that to you on the way to the photographer, so you had to keep checking it.

EET: What about timing verification?

Faggin: Early on we made some test patterns and measured their characteristic curves. This let us develop a set of normalized devices — building blocks that we could use over and over again in the chip — with known performance. I could work out delays by superimposing the curves for the devices and estimating the area between the curves to get charging times of the nodes. It was very much slide rule and graph paper.

EET: So, basically you created a cell library?

Faggin: Yes, basically.

EET: What happened when the wafers came back?

Faggin: There were no automated probe stations. We had a wafer stage with a bunch of probes mounted around it, with screws to control the X, Y and Z location of the probe tip. If you wanted to see the signal, then you had to probe a bonding pad or an internal node this way, and then hook up an oscilloscope to the probe. No logic analyzers, either.

The first lot of wafers I received had been misprocessed. But we got a new run in mid-January, and except for a couple of minor bugs it was fully functional. So January 1971 was the birth of the 4004. There was still a lot of testing to do, of course. I had to develop my own test patterns, with a pattern generator I'd appropriated from the memory folks. I added to that a bank of switches and a paper tape reader. I had to have a test strategy that would let me check all the circuits in a CPU from a cold start with just that and a bunch of scopes. It had to be systematic.

EET: So already at the advent of the microprocessor, design included floor planning, maintaining multiple views of each block through design, placement and routing, and tight coupling between those processes. It seems like the 4004 was the inception of a methodology as well as a chip.

Faggin: In a way, yes, that's right. While I was working on the 4004 Hal Feeney was working on a different, 8-bit controller design from Datapoint. After the 4004 I inherited that project, and applied the methodology from the 4004 to producing that chip. It scaled, and Hal and I were able to complete the 8008 in a very similar way.

EET: Does it seem strange that the EDA world still seems to be converging on some of the ideas — like optimizing logical, schematic and layout views of a design simultaneously — that were introduced in the early '70s?

Faggin: Not really. Remember that I was working with a very small number of gates. I ran a little calculation the other day, and in today's processes a 4004 would fit under a bonding pad. And I had no tools but a slide rule, really. I had to have a process that I could do in my head and still keep track of things. There was no room in the schedule for a rework: The design had to be right the first time.

So I was very focused on what I needed to get the design done. Often these days that's not the case. I think often it's not the designers who are making the tools. The tool developers may talk to designers, but they don't really do design. Maybe that has made a difference.

Ron Wilson is editorial director of Integrated System Design, a sister publication of EE Times.