Mitsubishi's 0.18-micron SOI CMOS technology overcomes the floating-body and hot-carrier effects that have hitherto made SOI unsuitable for high-voltage operation, said Shigeto Maekawa, group manager at Mitsubishi's ULSI development center in Osaka, Japan.

Mitsubishi plans to use the technology to make such communications ICs as a 2.5-Gbit/second multiplexer/demultiplexer for synchronous digital hierarchy and Sonet, said Maekawa, but he declined to say how soon.

While another company has reportedly developed a 2.5-volt dual-oxide SOI process, Mitsubishi is the first to develop an SOI CMOS process featuring the more common 3.3-volt supply, Maekawa said.

Mitsubishi employs hybrid trench isolation to create a stable process. "Hybrid trench isolation is the combination of partial trench isolation and full trench isolation," Maekawa said. "This device structure is rare — a Mitsubishi original."

On the parts of the chip with partial trench isolation, a thin SOI layer remains under the gate oxide and the bodies of the SOI MOSFETs are fixed automatically, enabling high-voltage operation. Full trench isolation is used between the n-wells and the p-wells, which frees the device from latch up, the company said.

"We were able to fix the floating-body effect with hybrid trench isolation," Maekawa said. "By suppressing the floating-body effect, we were able to assure the hot-carrier reliability. In addition, we also assured gate oxide integrity for dual-gate oxide."

No kinks

Mitsubishi's data also shows that it suppressed the kink effect, a floating-body effect that occurs on analog devices. Tests at Mitsubishi show that a circuit running at room temperature and 3.465 volts would achieve an operational lifetime of 20 years, Maekawa said. When the self-heating effect is taken into account, the lifetime is currently about 5 years, he said.

Mitsubishi has used the technology to develop 4-Mbit SRAMs that delivered "fantastic" performance and work well with RF and analog elements, said Toshiaki Iwamatsu, senior engineer at Mitsubishi's SOI advanced device department, in a paper presented recently at Semicon Japan.

"Hybrid trench isolation SOI technology is thought to be one of the main countermeasures to . . . release [a] high-performance system-on-chip," Iwamatsu said.

The SRAM featured a 5.2-nanosecond access time at a supply voltage of 1.2 volts and a standby current of 9 milliamps, dropping to 4.8 ns at 2.5 V and 6 mA, he said.

"Standby current was normal to that of off-current MOSFETs and the yield for the SOI is also the same as that of bulk SRAM," Iwamatsu said.

Mitsubishi estimates a 13-to-20 percent speed ratio improvement compared to bulk circuits at 1.8 V for inverters NANDs, for example.

For RF characteristics, SOI's lower junction capacitance and reduced electromagnetic induction current produced a 20 percent higher maximum oscillation frequency compared to bulk.

"Of course, we are developing next-generation SOI technologies including 0.13-micron SOI and beyond," Maekawa said.