Pipeline Master offers scheduling inside pipelines. As such, it transforms the number of stages in the pipeline and assigns operations, or logic, to each stage. Designers of chips with heavily pipelined architectures can thus try various implementations and evaluate latency, performance, power and area trade-offs.

Get2Chip chairman Bernd Braune described the offering as "the world's first highly optimized automatic pipeline synthesis solution."

Not so fast, said Tom Ferry, vice president of marketing for the physical synthesis group at Synopsys.

"Synopsys has provided designers with pipeline optimization techniques for many years," Ferry said. "Automatic pipeline insertion and pipeline retiming have been used by many Synopsys customers successfully. I do not think anything in Get2Chip's release changes the competitive landscape."

Like all synthesis startups, Get2Chip has a tough job competing with Synopsys, which holds an 87 percent market share in ASIC synthesis, according to the latest market figures from Gartner Dataquest. But Get2Chip claims that Volare is currently being used by about a dozen companies, and is supported by all major ASIC vendors.

David Knapp, chief technology officer of Get2Chip, said his company's pipeline scheduling is very different from the pipeline retiming offered by Synopsys. "Retiming moves registers over gates, giving you a fine-grained control," he said. "We do a coarse-grained scheduling of operations. For example, we'll move a multiplication from stage one of a pipeline to stage two of a pipeline."

This kind of scheduling greatly facilitates resource sharing, Knapp said. But its course-grained nature means "you don't get the last picosecond that you'd get out of retiming," Knapp acknowledged. Get2Chip's retiming capabilities are "limited," he said, and have primarily been implemented at the request of a single customer.

Knapp also acknowledged that pipeline rescheduling is not unique, and that Synopsys' Behavioral Compiler is one product that offers it. But Get2Chip has broken new ground in terms of its timing accuracy, he said.

"We do detailed, bit-by-bit timing of finite state machines, multiplexers, random logic, and wire-load models," he said. "We manage things like data and control hazards inside pipelines. We can handle loops nested inside pipelines for managing stalls."

Pipeline Master is aimed at high-performance, low-power applications such as networking, wireless telecom, and processors, Knapp said. Chips serving these applications often use pipelines as a way to get high performance.

Pipeline Master currently accepts behavioral Verilog input. Get2Chip offers a translator that accepts Superlog, and is working on a VHDL synthesis capability. Pipeline Master is tightly integrated with Volare, and runs concurrently with Volare's architectural synthesis. It can output RTL or gate-level code. A graphical user interface provides a block diagram and shows the distribution of hardware resources.

Pipeline Master is shipping now on Unix and Linux platforms for $25,000.