Version 2.0 improves the software's LogicLock block-based design capability, adds the FastFit compiler option, boosts network compilation performance and has enhanced debug capability, said Tim Southgate, vice president of software and tools marketing at Altera. The company has added board-level verification tools and support for Altera's MAX7000 PLDs, he said.

Southgate said Altera enhanced the algorithms of its LogicLock block-level design methodology so that designers can better control interactive block placement. Users can set performance targets for particular blocks — optimizing I/O timing at the block level, for example — and the tool assists users in achieving optimal floor planning.

"It not only lets the user lock down better performance but gives, on average, a 15 percent improvement in performance itself," he said. "Users assist in floor planning the design, but results are better transferred to the place and route tools. This [LogicLock] version is much more automated."

Compiler option

Altera has also added a compiler option. Called FastFit, it speeds compile times on average up to 50 percent over the default compile settings in Quartus II version 2.0, said Peter Woo, director of software tools marketing.

Woo said FastFit dictates how hard the compiler looks for solutions during the place and route phase. Typically, he said, the feature will be used when designers are trying out different layouts. When they settle on the best layout, they can simply turn off the option. FastFit can also be used on non-critical areas to speed the overall design process.

New compression techniques reduce the data transferred across networks, yielding up to a 50 percent reduction in compile times compared with version 1.1. The company used the same techniques to reduce the disk space usage of the Quartus II software by 60 percent in Unix machines, making it possible to transfer the suite over the Web and maintain it on networks more efficiently.

Altera has also added technology to Quartus II that lets users incrementally route an internal node to an unused pin for analysis without affecting a design's original routing, timing and design files.

New Ibis I/O performance models for the latest devices are customized using the I/O standard settings for each pin in the design, easing third-party tool analysis, Southgate said. Altera has added symbols for its newer devices so they can be recognized in schematic-capture tools.

The Quartus II version 2.0 upgrade will ship free to users with active subscriptions in February. For new users, the suite is priced at $2,000, running on Windows and Unix platforms.