Spanish researchers Juan L. Aragon, Jose Gonzalez, Jose M. Garcia and Antonio Gonzalez noted that increasing the size of the branch prediction hardware begins to yield diminishing returns after a certain point. Thus the researchers proposed a generic branch prediction reversal unit (BPRU) that includes "data values to assign confidence to branch predictions, attempting to use different information from that employed by the branch predictor.

"This can be very efficient in different scenarios — such as branches that close loops, list traversals or pathological if-then-else structures — where the involved branches may not be correlated with previous history but may be correlated with data values," the researchers reported. "Confidence metrics show that the BPRU is able to label as 'low confidence' 43 percent of branch mispredictions, whereas selective branch inversion assigns low confidence to just 26 percent of branch mispredictions."

Speaking on "Heterogeneous Computing," Tracy D. Braun of Noemix Inc. (San Diego) and Howard Jay Siegel and Anthony A. Maciejewski of Colorado State University cited a need to develop software environments that automatically map and execute applications expressed in a machine-independent, high-level language to facilitate usage of heterogeneous computing suites. Developing such environments will increase software portability and increase the possibility of deriving better mappings than users themselves derive with ad hoc methods.

Joe Bannister, Joe Touch, Purushotham Kamath and Aatash Patel of the University of Southern California-Los Angeles proposed an optically boosted router that would better leverage optics for packet switching. The booster "is an inexpensive, straightforward upgrade that can be deployed readily in a backbone Internet Protocol network and provide optical processing throughput even when not deployed ubiquitously," they reported.

Italian researchers advocated a performance model using a deterministic and stochastic petri net for performance analysis of mobile packet data services sharing a common GSM/GPRS cellular infrastructure with mobile telephony services. "The DSPN model is flexible and computationally parsimonious, allowing accurate estimation of a variety of performance metrics for the considered system," they said.

Rajiv Ravindran and Rajat Moona of the Indian Institute of Technology presented a simulation-driven program profiler. "First, we have used a retargetable functional simulator generated from a high-level processor description language, Sim-nML. Second, through a programming interface, we have provided a mechanism for implementing customized profilers. Thus, we do not tie the profiler to a particular instruction set or to specific profiling techniques," they reported.

William D. Gropp of the Argonne National Laboratory observed in his presentation that the Message Passing Interface addresses crucial issues in providing a parallel-programming model. "MPI's performance comes partly by accident; the two-level memory model is better than one-level memory model at allowing the programmer to work with the system to achieve performance. But a better approach needs to be found," he said.

Gropp said two branches seem promising: One would develop programming models targeted at hardware similar in organization to what exists now, and the other looks to co-develop both new hardware and new programming models. "Another major need is to make it harder to write incorrect programs," he said.

Vivek Sarkar and Julian Dolby from IBM's Thomas J. Watson Research Center (Yorktown Heights, N.Y.) said multiprocessor scalability, efficient fine-grained synchronization, efficient memory management, exploitation of high-performance processors in servers, efficient library and component usage and continuous availability are critical server requirements that must be addressed more effectively by future virtual machines for Java.

Additional coverage of the Eighth International Conference on High Performance Computing is available at EETimes.com.