Mosys Inc. has developed 1T-SRAM, which its says is less error-prone than standard SRAM. And startup Iroc Technologies offers chip makers ways to protect against transient errors in both logic and memory in system-on-chip designs.

For memory, the company offers a suite of IP that includes a code generator, code bits and error logic that is said to keep errors to zero. To combat errors in logic, Iroc has come up with another special cell to catch and fix faults before they make their way to the registers, at which point they can cause failures.

For its part, Mosys (Sunnyvale, Calif.) is pushing technology it says will significantly reduce its own soft-error rate by adding error correction to its memory cell. It will offer the technology to customers in macro form.

Transient errors are usually associated with soft errors, which are caused by alpha particles emitted by anything from packaging to cosmic rays from deep space. But transient errors can also encompass the ill effects of cross-coupling, said Eric Dupont, president and chief executive of Iroc Technologies (Santa Clara, Calif.).

Memory circuits have been deemed most vulnerable to transient errors, but there's mounting evidence that logic may not be immune. Just as they can flip a bit in a memory cell, an alpha particle or cosmic ray striking a logic node can create a transient pulse that resembles a signal and then propagate through the logic network, causing a system error. These pulse widths typically range between 500 and 900 picoseconds, Dupont said. "The physical phenomenon is exactly the same: There is no reason why logic transistors are less impacted by transient errors."

Using a Sparc-compatible processor developed by the European Space Agency for a test case, Iroc found that logic's sensitivity to transient errors rises gradually as the linear energy transfer of radiation particles rises. The experiment was done on a processor running at 40 MHz.

Rising clocks, greater worries

More worrisome for logic designers is what Iroc has extrapolated from the test case. According to its simulation of the same processor running at 400 MHz, the company said the processor's sensitivity to transient errors will be similar to or even surpass that of memory as a result of the higher clock speeds.

Dupont, however, said conclusive results won't be achieved until Iroc runs tests on actual hardware. "We need to validate it to see if it is real or if this is a borderline effect, because we're at the maximum performance of the simulation," he said.

Still, Dupont said he's confident there is enough evidence to support the conclusion that logic is prone to more failures as the clock rate rises. He attributed this to the shorter intervals between clock edges, where the errors can be captured and treated as valid bits. "As we have more clock edges, the probability that you will latch onto a transient pulse goes up," Dupont said.

Among those most at risk of transient errors in memory cells are makers of disk drives, where access times can be measured in single-digit nanoseconds. That is why companies like Seagate, Maxtor, Western Digital and Quantum have strict reliability requirements, often mandating ultralow failure-in-time (FIT) rates of 50 to 100 per megabit of memory, Dupont said. (A FIT of 1 indicates a single failure for a billion device hours.)

Iroc maintains that the technique it uses to combat errors in logic can be implemented without the speed degradation caused by building in time-redundancy circuitry, a way of duplicating information and observing the outputs of a circuit at different times to ensure that the data is reliable. "We stop the system only when there is an error vs. adding specific blocks on the critical path," Dupont said.

The error-protection cell can add 5 to 10 percent die area to a design. Iroc is offering to build in safeguards early in the design process, inviting designers to work closely with Iroc on mechanisms that can vary depending on application, device speed or environmental conditions. "It's not a pushbutton tool," Dupont said.

Transparent fix

For its part, Mosys has boasted a substantially lower FIT rate than standard SRAM even for its original cell. With the latest "transparent error-correction" technology, Mosys said it has brought the failure rate down to a negligible 10 FITs/Mbit.

Mosys says its original 1T-SRAM cell had enough room to squeeze in some error-correction circuitry without increasing the cell size or affecting its SRAM interface. Mosys elected not to minimize its cell size so as to keep its soft-error bit rate relatively low. By building in the error correction, the issue becomes moot. "The fact that we're adding internal error correction means we can now tolerate SER [soft-error rate] by 2x because the circuitry works to reduce SER by 10,000x," said Mark-Eric Jones, vice president of IP at Mosys.

The technology should prove beneficial in manufacture since there's no need for laser repair; the error-correction circuitry "automatically detects a bad bit in any word and repairs it at the time the data is read," Jones said. "Today 50 percent of a chip can be embedded memory, and it's becoming the largest contributor to quality in terms of yield, soft-error rates and reliability."

Initially, Mosys is offering its new 1T-R technology as custom macros for select customers using 0.13-micron design rules. Jones expects the first standard macros to be out by year's end.