The concept of 4G wireless technology is already taking shape in the minds of engineers, even though the battle to implement 3G has barely begun. Initial discussion of 4G networks has sparked widely differing ideas on technical specifications and applications; however, consensus does seem to be forming. Depending on the source, 4G will incorporate multiple wireless transfer standards (Bluetooth, WLANs, cellular signals), as well as other spectra like TV and radio, all using data rates that will measure anywhere from 5 Mbits/second to 100 Mbits/s and beyond. Naturally, all this data needs to be accessed and sent using a device small enough to fit in your pocket.
Today's dominant wireless communication technologies, including cellular, cordless, GPS and ISM-band systems, require significant innovations in their application technologies if they are to expand beyond their current markets and reserve their spots at the 4G table. As portable wireless communications devices such as digital phones and PDAs add capabilities and meld into a single handheld device, the need for highly integrated radio frequency (RF) designs with lower cost becomes even more urgent.
In recognition of the trend toward integration in the wireless world, engineers at GCT Semiconductor have developed a patented direct-conversion RF architecture that uses the CMOS fabrication process.
CMOS historically has served as a substrate that provides low materials costs and high manufacturing yields, but it has earned criticism from users and designers alike for consuming more power than BiCMOS. However, RF CMOS' achievable performance and cost benefits, combined with power-consumption levels that meet specifications, make it well suited to high-speed wireless applications. Higher levels of integration that support 4G should be possible without relying on more expensive and lower-yield processes and substrates. An examination of the RF system itself helps explain why.
CMOS block
Generally, an RF system consists of two subsystems: the RF front-end block and the baseband digital signal processing (DSP) block. It's possible to deploy the baseband DSP block with low-cost and low-power CMOS technology. However, the industry has not been able to integrate the RF front end using CMOS, because that technology's fundamental limits in speed and noise characteristics fall below the specs required by popular RF communication systems.
Take, for instance, the PCS hand-phone system. It operates at a frequency above 2 GHz, but current CMOS can reliably support operations up to 1 GHz only. Therefore, the RF front-end block is typically implemented using bipolar, silicon germanium or BiCMOS technologies, which offer better speed, power-consumption levels and noise characteristics than CMOS but are more expensive and do not yield as well. Thus, in order to achieve the cost savings, high yields and tight integration that 4G eventually will require, the ability to integrate the RF front-end block with the baseband block using CMOS is an early design advantage.
As wireless LANs, personal-area networks and cellular systems move toward 4G, demand for multimode (two or more standards operating on the same frequency) and multiband (two or more standards operating on different frequencies) solutions is increasing. As such, it seems inevitable that a multimode/multiband standard will emerge. If this proves to be the case, a direct-conversion architecture that is cost-effective and includes integration benefits will provide the best means for serving these demands, and will offer the lowest bill of materials, the smallest form factor and the most efficient manufacturing process (CMOS).
There's a slight glitch, though: Existing direct-conversion architectures have problems-direct-conversion (dc) offset and flicker noise-that, unless corrected, will prevent them from performing on par with the superheterodyne structure. dc offset is a by-product of direct conversion that occurs as the LO signal makes its way to the input of the mixer, which generates a dc offset frequency that can overload filters and gain amplifiers, hindering performance. GCT's engineers have developed a direct-conversion architecture that solves the fundamental problems of dc offset through dc algorithms that can suppress the offset enough to prevent saturation of the receiver and performance degradation. In addition, the sensitivity and 1/f noise problems have been remedied by optimally controlling a number of amplify-and-filter stages in the receiver chain.
Single-chip answer
Designing out these problems allows the company's direct-conversion single-chip RF system to operate at frequencies well above the 1-GHz threshold. Further, the reduced component count and the use of CMOS ease the integration process and cut size and power consumption.
As a result, GCT's single-chip RF communications system consists solely of the following components: a transceiver for receiving and transmitting RF signals; a phase-locked loop for generating 2N-phase clock signals having a frequency of 2 (f/N) smaller than a carrier frequency (N is a positive integer as a phase number and f is the carrier frequency); a demodulator for mixing the RF signals having a frequency reduced by the carrier frequency and comprising a plurality of two input mixers; and an A/D converting unit for converting the RF signals from the demodulator into digital signals.
Continuing this trend in size, power and component reduction will be critical as 4G draws closer. RF CMOS is the most cost-effective solution for both 3G and 4G, due to its higher integration density, higher-speed performance and larger wafer sizes. It satisfies the market demands for low cost, low power consumption and high integration for wireless applications of 1- to 3-GHz bands today. Expect this technology to continue to be integral to the development of wireless communication technologies in the future, regardless of how the 4G standard is developed.
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