Payne was not saying he'd found the universal system-on-chip (SoC) architecture. Such claims are grand enough to be left to marketers. But he did make a fascinating observation about a category of applications near and dear to Philips: those that process streaming media.

At one extreme, a cell phone handles data streams. But the data rate is sufficiently small that you need draw no architectural conclusions from the data format. Not so video processors, network switching gear, graphics engines and storage-area network devices. In many of these applications, that the data arrives in nearly continuous, often undelimited streams at high bit rates has profound implications for the architecture that must process them.

In Payne's model, data enters and leaves such an SoC through streaming pipes, the particulars of which are not architecturally important. Once in the chip, the data streams are processed by stream-oriented-that is, data-flow-oriented-processing elements. An array of such elements, either homogeneous or heterogeneous depending on the needs of the applications, is orchestrated by an industry-standard RISC CPU.

The model is based on a fundamental distinction. The control flow in such a stream engine is inherently nonlinear: It is conditional and asynchronous, depends on external commands that are separate from the data streams and perhaps depends as well on fields extracted from the data streams. To do this, a controller must be good at classification, conditional changes in control flow, interrupt response. And, as Payne noted, it must be able to refill its caches rapidly in response to unpredictable changes in control flow.

Stream processors are entirely different. Ideally they would be pure flow-through data processors. But the realities of algorithms and implementation ensure that these engines will usually be separate blocks in separate clock regions with FIFOs in between. The memory needs of these blocks relate to FIFO handling.

Payne concludes that control-oriented architectures and streaming architectures are not interchangeable. The attempt to implement both using the same base-by extending a RISC CPU, for instance-is a first step in the wrong direction.