Today, the designer has little to no design latitude for efficiently adding another standard or increasing a phone's functionality. This issue moves to the fore as designers of third- and fourth-generation products worry about implementing major new functions on basically the same DSP and fixed-function ASIC material used in earlier generations.

The FPGA-based approach is quickly eliminated because it is power-hungry, cost-prohibitive and overly slow, with reconfigure times of seconds and milliseconds. Compared with an adaptive computing solution, the FPGA solution incurs a high area penalty, of 125:1 on average, precluding its use in any cost-constrained environment.

Adaptive computing provides the needed IC alternative with the speed of an ASIC and the software flexibility of a DSP. Within the ACM's adaptive architecture, dynamic algorithms are rapidly mapped to dynamic hardware resources. The ACM adapts itself to each algorithmic task on demand and configures itself for the exact hardware needed.

Binary files used for configuring and sequencing the adaptive computing fabric are stored in on-chip cache, supporting the ACM's real-time requirements. A controller oversees the loading and unloading of binary modules from the cache onto the ACM's fabric, or matrix, where the actual computing is performed.

This new approach to silicon is based on Campbell's Corollary to Moore's Law: efficiently using transistors to dramatically increase performance and greatly reduce the number of transistors needed. The corollary, created by Chips & Technologies founder Gordon Campbell, is dead-on for the world phone.

Paul Master is Vice President and Chief Technical Officer of Quicksilver Technology Inc. (San Jose, Calif.).