The concept is clear, but the sticky part, as always, is the execution. Part of the dilemma is that the transition involves a dirty word nobody in the industry likes much: revolution. The architectures and processes being investigated for next-next-generation memories may seem awfully far out to the traditionalists.

Take magnetoresistive RAM as an example-a superfast nonvolatile memory that's capable of achieving DRAM densities, will hopefully be compatible with a logic process and will feature nondestructive read-write characteristics. MRAM may not be on store shelves yet, but it exists today as one of the leading contenders for the memory of tomorrow.

At the upcoming VLSI Symposium in June, Motorola Inc. will discuss 1-Mbit test chips made on a 0.6-micron process and lay out a road map to .18 micron. The company will put out samples toward the second half of next year and move into volume production in 2004.

"They will be small densities, just a few megabits," said Saied Tehrani, a leading researchers on Motorola's MRAM project. "Our interest is for embedded applications, so depending on the embedded scenario it will range from 4 to 16 to 32 Mbits."

Motorola has been working on MRAM for several years. IBM, Infineon Technologies and, more recently, foundry Taiwan Semiconductor Manufacturing Co. are also among those in the race to develop this conceptually promising memory, which is touted as a replacement for DRAM, flash and static RAM alike.

The basic attraction of MRAM is its speed and nonvolatility. IBM Corp. has measured MRAM write times down to 2.3 nanoseconds. That's more than 1,000 times faster than the fastest nonvolatile flash and is 20 times faster than nonvolatile ferroelectric memory-a potential competitor. MRAM access times are as fast as 3 ns, or 20 times faster than DRAM. And since such reads require only 2 milliamps, MRAM consumes less than 1/100 the energy of DRAM, according to IBM research.

The first devices will find applications in such areas as satellites, portable medical electronic equipment and advanced, third-generation cell phones. The MRAM's resistance to radiation is one of the reasons it is also considered a prime replacement for SRAM, which is expected to suffer more and more from density-induced soft-error rates as it scales below 0.1 micron.

Working within the stringent production requirements of MRAM, such as reliably achieving an 8-angstrom-thick oxide across a 200-mm wafer, has been one of the toughest tasks at Motorola.

"When we got into MRAM in 1995, we identified that as one of our biggest challenges," Tehrani said. Now the job has evolved into a "manageable aspect" of the MRAM process, though it is too early to say whether it will definitively remain so in a volume environment. "But there is nothing that shows up as a significant risk at this point that would prevent us from getting it to volume while controlling the thickness."

So should the flash and SRAM guys be worried? Not yet, they say. "The industry has used SRAM for more than 20 years now, and yet almost every few weeks there's an announcement of a new memory technology," notes Mark-Eric Jones, vice president and general manager of intellectual property at MoSys Inc., which developed a single-transistor (1T) bit cell for SRAM about three years ago. "Very few of them ever make it to volume production."

With the time line of MRAM and other novel memories-such as the Intel-backed Ovonic Unified Memory (OUM)-most likely five or more years out, Jones believes there is plenty of life left in today's architectures. Some of the problems associated with traditional 6T SRAM, such as increasing soft-error rates, are being handled by evolutionary architectures, such as MoSys' 1T-SRAM-R. According to Jones, this technology offers four-orders-of-magnitude improvement over traditional SRAM soft-error rates. Other SRAM designers, such as Virage Logic, say the six-transistor structure still has legs. At the 90-nanometer node, however, companies will need to implement stronger safeguards against soft errors and that will happen across three different realms, said Shakeel Jeeawoody, a technical-marketing manager at Virage.

"TSMC, for instance, is looking at the process level-where it will do a triple well and some different things with the dielectric. Virage is looking at the memory-design level. And when you are building a system-on-chip, you can also design in some system-level techniques to guard against soft errors," he said.

Flash providers are also sleeping well at night, knowing that nothing dramatic is on the horizon to make inroads into their markets as yet. At Silicon Storage Technology, developers are sticking with the company's split-gate multilevel-or multibit-cell storage technology as a way of scaling through the nodes to denser and cheaper memories.

"We have a much thicker oxide associated with our tunneling and, therefore, better charge retention," said Michael Briner, senior vice president of SST's application-specific product group. "As you store more and more states, then the charge per state comes down. So data retention is a much more stringent requirement for the fundamental ability to store the data and be able to retrieve it."

SST is currently migrating to .18-micron design rules and will go to .13 micron in one and a half to two years. That transition will bring the voltage down to 1.8 V, with an optional 3-V part for compatibility with legacy products. "We still have a lot of scalability to our tunnel oxide [which is about 200 angstroms thick], assuming there will be some fundamental limits in the range of 80 to 100 angstroms," Briner said.

Looking over the landscape, Martin Peisl sees something of a gold rush for that perfect nonvolatile memory. "Everyone is popping up with a different concept," said the senior director of specialty DRAM marketing for Infineon, which is working on both MRAM and ferroelectric RAM (FeRAM).

Bear in mind, Peisl said, that the flash world is comfortably cruising through the technology nodes. "[Flash] will be getting cheaper in the next few years and the only way of beating this road map is to be completely process compatible and have less masks," he said.