Through their joint venture, Fujitsu and AMD Semiconductor Licensing Co., Fujitsu (San Jose, Calif.) and AMD (Sunnyvale, Calif.) are working to double capacity with a flash memory cell architecture called MirrorBit. Each MirrorBit cell stores a full charge in each of two physically distinct locations. That contrasts with multilevel-cell technology, which stores fractional levels of charge in one location. Because each bit in a MirrorBit cell is stored in a different location, the bits do not interact with each other.

Besides boosting storage capacity, the MirrorBit architecture includes a write buffer that allows faster programming than current-generation flash products, plus a page read buffer that provides page mode access times of as low as 20 nanoseconds.

AMD has launched a 64-Mbit MirrorBit and plans to add a 256-Mbit part later this year.

Hitachi last month introduced the SuperAND flash memories, which combine single-voltage programmable flash cells with memory management, eliminating the need for external error-correction code and other memory-management algorithms, according to the San Jose company. The 128-Mbit (16-Mbyte) chips-available in 1.8-volt and 3.3-V versions with x16 organizations and in a 3.3-V version with a x8 organization-target cell phones, PDAs, digital cameras and mobile gear. Longer-term, Hitachi is working on 1-Gbit NAND flash chips that are expected to measure less than 100 mm2 and to feature a 10-Mbyte/second write speed. The chips are due sometime next year.

Hitachi is confident it can stack as many as nine 1-Gbit chips plus a controller on a Multimedia Card for a 1-Gbyte capacity-enough to store one hour of MPEG-2 video.

Based in Munich, Germany, Ingentix-a joint venture of Infineon Technologies Inc. (Munich) and Saifun Semiconductors Ltd. (Netanya, Israel)-is using Saifun's n-channel ROM (NROM) technology to build flash-based mass-storage products. They include a single-chip 512-Mbit device, based on a 0.17-micron process, that also contains two physically separated bits per cell. The device is said to be programmable at 8 Mbytes/s.

The NROM technology involves a localized trapped-charge device that uses oxide-nitride-oxide dielectric-retaining materials to enable the storage of two physical bits per cell.

Channel hot-electron injection is used to achieve a programming rate of 8 Mbytes/s, and erasing is done by means of tunneling-enhanced hot-hole injection, the company said.