Existing standard interconnects include Fibre Channel, SCSI and ATA (AT Attachment) for storage to processor interconnect technologies. New standard interconnects include Infiniband, Rapid IO and PCI Express. In addition, the PCI Industrial Computer Manufactures Group (PICMG) has created standard system interconnect specifications including PICMG 2.16, 2.17, 2.20, 3.1, 3.2 and 3.3.

Meanwhile, chip-to-chip interconnects such as UTOPIA (Universal Test & Operations Physical Interface for ATM), HyperTransport, SPI-4 (System Physical Interface Level 4), POS-PHY (Packet over SONET - Physical interface) and others are also in use to connect processing chips with each other and physical interfaces.

The alphabet soup of new interconnects might still be baffling, but what is clear is that each one performs a needed job particular to an individual application. As they migrate to higher performance levels, PICMG companies are creating standard industrial and carrier grade platforms to take advantage of these interconnects in a rugged and demanding environment that demands high reliability and open standards. The result will be a wide range of standard products with leading-edge interconnect performance from which embedded networking and telecom developers can choose.

Processor-to-processor interconnect technologies are used to move data between applications running on distributed processors. These distributed applications share data over interconnects and use protocols such as TCP/IP to insure the integrity of the data. Ethernet, the most popular processor interconnect, is a serial interconnect with performance from 10 Megabit to 1 Gigabit /second with IPv4 (Internet Protocol version Four), but is evolving to 10 Gbit/second and the new IPv6.

Some new interconnect technologies are included in this class of processor-to-processor interconnects. RapidIO is a point-to-point switched interconnect that can connect processing and memory chips. RapidIO over a single serial link provides 2.5 Gbit/second between nodes and can support multiple links for higher speeds. PCI Express (formerly 3GIO) is also a high speed serial interconnect between processing and I/O chip technologies that preserves software compatibility with the PCI bus.

Infiniband is seen as the up and coming interconnect in this space with performance starting at 2.5 Gbit/ second per serial link and reaching up to 10 Gbit/second with four links and 30 Gbit/ second with 12 links. While Infiniband is a processor-to-processor interconnect, it is also targeting processor to I/O device interconnect applications. Storage is the first I/O device targeted by Infiniband.

Processor- to-storage apps
Fibre Channel (FC) and SCSI have been the dominant technologies in the processor-to-storage interconnect space. These interconnects primarily connect the processing unit to the storage units, but have also been used to provide processor-to-processor interconnect in clustering applications where the storage units are shared between multiple processors.

However, Infiniband is expected to provide better scalability than SCSI or FC as a processor-to-storage interconnect. Serial Attached SCSI (SAS) is a new draft standard, which defines transmission of SCSI protocol over a Serial ATA (SATA) compatible physical layer and defines addressing of multiple target devices for the SATA protocol.

ATA and ATAPI (AT Attachment Packet Interface) are also used in processor-to-storage applications. Performance of these very popular parallel interfaces in desktop applications has been improved upon and now can provide up to 266 Mbyte/ second throughput. Serial ATA is being specified and designed to preserve the ATA programming model while providing a roadmap to increased performance with speeds up to 3 Gbit/second and reliability of a point-to-point hot pluggable interconnect.

While network interface interconnect technologies are not as widely known as those previously discussed, they are in wide spread use and are standardized in network processor chips and network interface devices. These include the UTOPIA, POS-PHY, SPI-4 and HyperTransport parallel interfaces with performances over 8-, 16- and 32- bits up to 1.6 Gbyte /second. These interconnects create the backbone for ATM and TDM networking protocols used in the wired and wireless telecom industry.

PICMG is a consortium of companies that work together to create standard specifications. These specifications enable an ecosystem of platform and module providers to jointly create standard embedded and telecom products that interoperate.

Current key standards contenders include existing Fibre Channel, SCSI and ATA for storage to processor interconnect technologies. New standard interconnects include Infiniband, RapidIO and PCI Express. PICMG has created standard system interconnect specs including PICMG 2.16, 2.17, 2.20, 3.1, 3.2 and 3.3. Chip-to-chip interconnects such as Utopia, HyperTransport, SPI-4, POS-PHY and others are also in use to connect processing chips with each other and physical interfaces. Source: Motorola

The PICMG 2.16 standard specifies a switched Ethernet interconnect supporting up to 1 Gbit/second using the 802.3ab interface, over a PICMG 2.0 CompactPCI backplane in a dual star configuration. PICMG 2.16 works best in applications that use protocols that run over Ethernet such as TCP/IP and want to integrate the cables used to connect the processors into the backplane of the chassis.

PICMG 2.17 specifies a switched interconnect in a CompactPCI backplane for the Star Fabric PCI to PCI and H.110 compatible bridging technologies over high-speed serial point-to-point links at speeds up to 2 Gbit / second. PICMG 2.20 specifies a full mesh high-speed serial interconnect in a PICMG 2.0 backplane.

PICMG 2.20.1 specifies a use of the 2.20 mesh for a Network Processing Distributed Fabric based on CSIX-L1 (Common Switch Interface Specification - L1). The PICMG 2.20 interconnect operates at speeds up to 3.125 Gbit /second across each point-to-point link to and from 18 slots for a maximum aggregate performance of up to 700 Gbit/second. All the PICMG 2.0 specifications such as 2.16, 2.17 and 2.20 are designed to follow the PICMG 2.0 6U x 160mm board form factor specification.

PICMG 3.0 is a new standard being developed called Advanced Telecom Computing Architecture (AdvancedTCA). It specifies a new and larger than CompactPCI PICMG 2.0 form factor for boards that are 8U high and 280mm deep. The AdvancedTCA PICMG 3.0 chassis supports up to 16 slots with full mesh backplane interconnect with four 2.5 Gigabit bi-directional links between each slot.

PICMG 3.1 specifies the use of Ethernet over this full mesh, while PICMG 3.2 specifies Infiniband, and PICMG 3.3 specifies Star Fabric interconnects. A new standard subcommittee for PCI Express called PICMG 3.4 was just established. Future PICMG 3.x standards for Network Processing Fabrics such as CSIX-L1 and other interconnects will be established later this year.

All of these AdvancedTCA PICMG 3.x standards specify the use of the full mesh backplane interconnect specified in the PICMG 3.0 base specification. The best use for each depends on the protocol a particular application can benefit from.

For example, a server comprised of many boards each with several general purpose processors all providing a distributed service such as a Web hosting or email will probably use the PICMG 3.1 Ethernet connectivity because Ethernet is the media used to connect web servers.

On the other hand, a file server application may use PICMG 3.2 and the Infiniband connectivity to provide the scalable connectivity to disks and processors. These standard interconnects in the new PICMG 3.0 form factor enable the embedded networking and telecom designers to choose one that best meet the applications needs in a specific carrier grade platform.