Version 2.1 packs new ASIC-design tool flow utilities such as a floor planner for advanced users, said Tim Southgate, vice president of software and tools marketing at Altera. For pushbutton users, several automated features increase design performance while shrinking chip area.

"With version 2.1, we've really focused on letting a guild designer get the best performance out of a complex design," said Southgate. "We have done a great job with Quartus' pushbutton flow as designs get more complicated, but now we have added features that allow users to incorporate their experience and knowledge into the design process to get the best performance out of their designs."

Peter Woo, Altera's director of software and tools marketing, called the new timing-closure capabilities Quartus 2.1's key enhancement. To cut down on design iterations, the company worked closely with third-party suppliers to ensure that their synthesis tools, along with Altera's own synthesis tools, dovetail with Altera's placement and routing technology, he said.

Automated functions

Further, Altera has added a pushbutton postsynthesis netlist optimization feature that Woo said will yield a 10 percent design improvement in 65 percent of all designs. To that end, Woo said, the company has added algorithms that automatically perform register retiming and logic duplication.

Woo said that the features, which can be toggled on and off, are targeted at novices or users who typically use Quartus' pushbutton flow. Advanced users who hand-tweak their designs will not likely see a performance gain. "If you have a decline in performance or zero improvement, you can just go back to the original netlist and the only thing you've invested is a small amount of time," said Woo. "But when we do see a gain it is a significant gain — about 10 percent."

The new version of Quartus also has a timing-closure interactive floor planner that provides designers with nine views of timing and placement within the device, said Southgate. Designers can view hierarchical timing relationships between various blocks in a design and can edit or create timing and placement constraints to optimize performance.

Altera has also bumped up the performance of its Signal Tap II logic analyzer so that the tool now tests multiclock designs.

Among the links to third-party tools, Quartus now runs with Conformal LEC from Verplex. Also, the tool now supports the Synopsys Design Constraints format and such design rule checkers as Atrenta's Spyglass and Synopsys' Leda.

A one-year license for Quartus 2.1 is priced at $2,000.