There is little question that the business environment during the past two years has been difficult. Since the second quarter of 2001, our business has remained relatively flat. While we see the same number of designs today, production volumes are generally lower than they have been in the past. At the same time, the FPGA-to-ASIC conversion market has cooled off as system manufacturers wait for their sales unit volumes to ramp up.

In a downturn of this magnitude, the key to the survival of any OEM is to develop products as efficiently as possible. Minimizing nonrecurring-engineering (NRE) costs is one of the most effective ways a silicon supplier can help its customers reach that goal. This issue has become even more important now that the market turnaround has been repeatedly postponed.

It is becoming increasingly probable that the market ramp, whenever it happens, will take place in 0.13-micron technology rather than in the 0.18-micron technology that predominated in 2001. That, in turn, will force ASIC developers to confront mask costs, which soar as high as $700,000 per set. At those costs, OEMs will require increasingly higher unit-sales potential to justify their investment. We believe that trend will drive ASIC customers to develop their products in high-performance gate arrays that offer fewer mask steps as well as much lower NRE costs.

More than ever before, customers are concentrating on inventory management. And many have switched to a "build-to-order" rather than the traditional "build-to-forecast" formula for purchasing. How can ASIC suppliers help their customers make this migration? One approach we have implemented is to enhance our short production lead times with a flexible delivery-lot-size program. Our ability to deliver unit quantities in increments of one wafer of production contrasts with minimum lot sizes of six or more wafers from most standard-cell vendors. A second strategy we have pursued is to increase our investment in the development of new silicon products that offer smaller geometries, new features and better performance.

The coming upturn will be similar to those the semiconductor industry has seen many times before. It will not follow a dramatic hockey-stick curve. Instead, we predict that the market will rise on a relatively steady slope in the historical range of 9 to 18 percent. Some FPGA makers say they see signs of an upturn. We believe the gate array and ASIC business will follow closely behind. Leading the turnaround will be silicon suppliers that can provide a solution that combines low unit cost and fast turnaround, while avoiding the skyrocketing NRE costs associated with traditional ASIC methodologies.