In these economically turbulent times, increasing efficiency and reducing risk while continuing to innovate are critical goals for companies looking to ride out the economic storm. Vendors of programmable-logic devices have driven innovation and provided a vehicle for efficiency and risk reduction by bringing to market denser, higher-performance products supported by extensive portfolios of intellectual-property blocks, including embedded processors and high-speed I/Os. Given the low economic risk offered by FPGAs, we can expect programmable logic to gain market share at the expense of ASICs.

By providing a programmable silicon platform that can be modified quickly to meet changing market conditions, FPGAs give product developers the crucial design flexibility they can't achieve with ASICs. Further, the mask costs, minimum-run sizes, complex tools and high labor costs needed in ASIC design do not exist in FPGA design. In fact, FPGA vendors are responsible for deep-submicron effects such as power distribution, test insertion and signal integrity that often plague ASIC designers.

Because not every design is successful, predicting the actual production volume of one can be difficult. Developing FPGAs with a conversion plan in mind allows a company to lower the risk of failure by beginning production in low volumes and scaling upward as demand dictates.

FPGA-based prototyping of ASICs is also becoming a common approach to lowering the risk of ASIC failure, creating a demand for large, high-speed FPGAs and the design tools needed to support them. Like ASIC design tools, FPGA design tools revolve around the core implementation tool chain, which includes synthesis, physical synthesis, placement and routing. With the increasing adoption of FPGAs for a wide variety of applications, we can expect the FPGA EDA market to expand.

As leading FPGA vendors have advanced their product portfolios, designers now use mature, extremely fast, reliable FPGA synthesis tools to achieve better-quality results in less time. Synplicity offers a second-generation solution that performs simultaneous detail placement, optimization and sophisticated routing estimation to solve the timing-closure problem.

In these uncertain times, maximizing product-development efficiency and minimizing risk become more important than ever. The adoption of FPGAs and the use of market-leading, proven FPGA synthesis tools offer systems companies the best opportunity to retain innovation in their products while increasing efficiency and minimizing the risk of extended development schedules and high up-front costs.