Today the industry relies on formalized interfaces among design, mask making, production and test. For example a GDSII tape communicates the design to the mask shop. A set of design rules communicates the process requirements to the design team.

But already, those interfaces are failing. "Specifications and design rules are no longer sufficient to guarantee a successful design," said Steven Carlson, senior vice president at mask maker Photronics Inc. "I would estimate that over 80 percent of the designs coming into the mask shop at 0.13 micron require additional work in order to produce yieldable masks. This is forcing a continuous communication between ourselves, the design team and the lithography team."

In come cases, Carlson said, design teams "come to the shop with a 0.13-micron design and then back off to a 0.15-micron design when they realize the complexities they are facing. Before we are through on these advanced designs, it is not uncommon to have a design meeting that includes not only the chip design team but the lithography team, the stepper people and the wafer-processing team as well. They will work together to cut down the risks and reduce the number of prototype spins."

The underlying problem is complexity. In the avalanche of data that the design team ships to the mask shop, all concept of how the design actually works — and, hence, what performance it actually requires at any given net — is buried. So the mask makers, in the absence of cooperation, are compelled to push every feature on every mask layer to its greatest resolution.

That means using the most expensive mask-writing equipment with the lowest throughput, performing the most exhaustive inspections and attempting repairs on every identifiable defect. And it means $1 million mask sets.

Often, much of this effort is unnecessary. "Some people are starting to ask whether all designs really need this maniacal push toward the lowest possible critical dimension," Carlson said. He cited a number of examples where increased information from the design team could save lots of money.

One involved maintaining critical dimensions on transistors. At 130 nm and below, the window between a transistor that leaks too much and one that switches too slowly is narrow indeed.

It takes the best work from the best available tools to maintain transistor critical dimensions throughout a critical net. It would be far easier to crack open the process window on non-critical nets, allowing slower switching times.

But the mask shop, where this decision could be made, often has no idea which nets are critical. So everything gets the full treatment.

A similar example comes up in mask inspection. At 130 nm and below, many defects that are detectable on the mask would be too small to print or would result in a feature on the wafer that would have no electrical impact on the circuit. But to decide whether to attempt to repair the defect, the mask shop would have to simulate the impact of the defect on the wafer (tools for doing so are now available from Numerical Technologies Inc.), extract circuit parameters from the simulation and then ask the design team if the new circuit was acceptable. Such information loops are rare today.

Neither does the situation change as the design moves from mask shop to production. Fabs today maintain a variety of steppers with a range of resolutions. Equipment cost, throughput and yield are highly sensitive to the feature size and toleration for defects in the design. Lacking detailed information from design teams about their actual needs for electrical parameters, process integration engineers have little choice but to tune the process for the most demanding requirements — at the greatest cost.

The situation does not change in downstream processing steps. "There is a limited understanding among chip designers about design/process trade-offs," said Wilbert van der Hoek, chief technical officer and executive vice president at Novellus Systems Inc. "This became apparent when we first launched copper interconnect.

"At first, designers thought copper was a resistance play, and they designed in the same way as before, but counting on lower resistance in the interconnect for improved RC time constants. But the process engineers discovered that they had dishing and erosion problems with the copper and that they were in fact losing a good fraction of the height of the lines. So the resistance they delivered was about what they had with aluminum in the first place.

"As chip designers adjusted to not getting lower resistance, they realized that less height in the interconnect lines meant less capacitance," van der Hoek said. "So they drove the process guys to specify thinner metal and took advantage of the lower capacitance to improve the RC constant. It was a dialogue."

There will be even more intense dialogues in the future, van der Hoek said. "For example, some integration schemes for low-k [low-dielectric-constant] dielectrics will only work if you have landed vias. But landed vias are more than just a design rule issue; they need to be thoroughly discussed with the design team to understand their impact on performance and density.

"Another example with low-k dielectrics comes from the fact that these films are very fragile. It may prove impossible to planarize the metal stack with chemical-mechanical polishing because of the stresses that [result] in the dielectric material. One alternative is electropolishing. But electropolishing tends to remove material more rapidly from large areas of metal than from small areas. It may be necessary for the layout tools to break a 20-micron-wide line down into a collection of much narrower lines in order to prevent its being polished away."

The issues continue through wafer processing and into test, where test engineers are already pleading for access to design information, particularly about the designer's original intent.

The problem in test is similar to the problem in mask inspection: When you detect a failure, how do you know whether it is a fatal problem, a problem that can be lived with or one that is irrelevant to the actual operation of the circuit?

Some test engineers make the distinction between digital test, which has historically looked for specific defect-caused failure modes in a chip, and analog test, which attempts not to inspect a circuit but to characterize it. Increasingly, faults in finished dice are delay faults or signal integrity problems. This is due to shifts in the nature of defects in the fabrication process, but it is driving change in test strategies.

Tests for stuck-at conditions are excellent for detecting open or shorted lines from particle contamination but are not very helpful in detecting delay faults or signal integrity problems caused by more-complex issues in 130-nm or 90-nm processes. But the kinds of tests that can detect a lengthened path delay or an unacceptable amount of crosstalk are heavily dependent on an understanding of how the chip is supposed to function, not merely on an understanding of its circuit structure. This is data that, if it was ever systematically recorded at all, resides in the design testbench — not in the sorts of design-for-test or automatic test pattern generation data that increasingly forms the information flow between design and test.

A two-way street

In mask making, lithography, wafer processing and test, experts are calling for increased dialogue with the design team. They emphasize that the information needs to flow in both directions: designers need to understand the costs of the decisions they make, and manufacturing and test specialists need to understand the designers' intent. Otherwise all parties will be forced into worst-case assumptions: The designers will receive design rules and design-for-test requirements that are crippling in size and complexity, and the mask makers, process integration engineers and test managers will be required to pursue every detail, no matter what its impact on the finished chip.

A new dialogue — and a common language — are becoming essential to progress.