The three companies worked together in Crolles, France, to complete the definition of process architecture, overall silicon architecture and libraries for this platform, according to Theo Claasen, chief technology officer of Philips Semiconductors.

The new 90-nm node platform will allow designers to get started on the development of a System-on-Chip (SoC) required for next generation low power and high performance consumer and communication systems in a fast and flexible manner, according to Claasen.

The three companies announced their alliance and plans "to align" their process technology development with TSMC's, four months ago under the "Crolles 2" initiative (see April 12, story).

It is not yet fully clear what "process alignment" with TSMC encompasses. It could go so far as TSMC providing the three chip giants with base process technology while Philips, STMicro and Motorola engineers focus on developing a wide variety of cells, process extensions and higher-order design blocks for internal and external use.

The newly announced support for system-on-chip comes in the form of a common library of cells which, unusually, will be shared by the three companies. However, the companies have not disclosed any processors or DSP cores that have been proven on the process technology. Full cores would be necessary for practical SoC design but cells allow the development of cores.

There are two standard cells libraries, optimized respectively for performance and density, offering a selection of more than 1,000 cells with up to nine routing layers. There are also I/O cells, embedded memory arrays and ROM compilers, the companies said.

Claasen made it clear that what is being made available today on the joint 90-nm design platform does not include cores but only cell libraries.

Asked about potential problems of metal migration and other process failures that may happen as a result of moving to 90-nm process geometries, Claasen said, "I don't think that the 90-nm itself will present an intrinsic hurdle. But we can find out how reliable and cost effective we can make the 90-nm process to be, only after we start designing real products and producing them in volume." He added: "That's why it is very important for us to make the 90-nm node design platform available now."

In April 2002, Motorola, Philips and STMicroelectronics announced an alliance to jointly develop future generations of CMOS technology from the 90nm node down to 32nm over the next five years, with the participation of TSMC for processdevelopment and alignment. By using the same design platform for manufacturing chips in fabs both in Crolles and TSMC's Hsin-Chu, Taiwan, "We think we can do the cost learning much more quickly, too," said Claasen.

Under the agreement, TSMC has been kept up to date on the definition of a process for the 90-nm design platform, and the company has been given the access to cell libraries, necessary to build test chips.

At the time of the partnership announcement for the joint CMOS process development earlier this year, Shang-Yi Chiang, senior vice president of research and development at TSMC, said, "There are other processor or DSP vendors developing a deep submicron technology on 300-mm wafers. But we've chosen to work with ST and Philips because they can cover SoCs in a very wide range of products including consumer and communications." Chiang added, "They are in the best position to identify initial winners for SoCs that will require a 90-nm process technology."

Philips, Motorola and ST are planning to add to the initial 90-nm design platform further extensions, including SOI silicon-on-insulator versions and high-performance integrated passive devices, "before the end of this year," according to Claasen.