Reconfigurable logic relies on reprogrammable digital circuitry (usually realized in SRAM-based FPGAs or CPLDs) to allow run-time modifications to a digital system. In theory, reconfigurable logic allows design teams to re-architect entire systems even after they've been installed in the field, or for a single chip to be shared among many system applications. Reconfigurable logic represents a fascinating possibility for systems design, but it requires designers to enter new and uncertain territory, where logic may change hundreds of times per second. Reconfigurable logic does not touch any system processor directly — just task-specific logic around the processor.

Configurable and extensible (tailorable) processor cores, by contrast, are a combination of hardware and software IP that give system developers the ability to tailor processors for better performance in specific applications. The system architect specifies new sets of hardware primitives — instructions, register files, and memory systems — ranging from simple, specialized bit-field operations to complex vector coprocessing units with wide data paths. The software environment — the compilers, assemblers, RTOSes, libraries and simulators — is extended in lockstep with the hardware. The designer then incorporates the processor hardware into the final chip design, but the design remains "soft" through the processor's natural programmability. The application program becomes a cycle-by-cycle configuration of the selected hardware primitives.

Tailorable processor cores, like Tensilica's Xtensa processor, provide many of the same design benefits as reconfigurable logic — reuse of chip designs and rapid, cheap adaptability — but in a different way. By tailoring a processor core, a system-design team can imbue a processor with more than enough processing capability to handle the processing tasks of some application domain so that the executable algorithms will run in software without any task-specific hardware-acceleration blocks (and often without even assembly-language programming). Although not as open-ended as reconfigurable logic, which allows the complete rewrite of task-specific logic on the fly, the use of tailored microprocessors allows substantial reconfigurability through the more conventional approach of software upgrades. Thus upgrading a system to meet new standards specifications, to add features or increase performance, or to correct a design flaw merely requires that the flash memory used to hold the system code be reprogrammed, a technique already widely in use. Consequently, design with tailored processor cores more closely resembles conventional system-design techniques than does the reconfigurable-logic design approach.

Although quite different, these two design techniques are not incompatible. For example, users of configurable/extensible processor cores routinely map the processor hardware into field-configurable logic for prototyping and low-volume manufacturing, to get the benefits of both low development cost and high design productivity. However, each design technique has a price.

Reconfigurable logic carries both a manufacturing price and a performance price. FPGAs and CPLDs are significantly slower, more expensive and draw more operating power than ASICs with equivalent functions. The delay of the programmable signal-routing matrix can completely swamp the delay of the gates themselves. The area of the programmable interconnect, the generic logic functions and the overhead of the RAM-based configuration mechanism inflate the transistor count by more than 10x, compared with dedicated logic, with a corresponding increase in die cost. The power also increases with increased capacitance and die area. Thus, reconfigurable processors are best applied when the target application is unknown, and low prototyping costs are more important than low manufacturing costs.

Configurable processor cores also have a cost, in terms of design complexity. Many system design teams are still unfamiliar with augmenting a microprocessor's instruction set and may not wish to make the small effort needed to learn the additional design techniques. Moreover, the benefits of reprogramming a configured processor are clearest when it is part of an application-specific chip focused on a specific class of application. It is more difficult to have a "universal off-the-shelf chip." Therefore, configurable processors are best applied where designers have some foreknowledge of the target applications.

Chris Rowen is CEO of Tensilica Inc.