Connector manufacturers have learned that as backplane transmission speeds move from 2.5 Gbits/s to 10 Gbits/s, system designers have to look at the performance capabilities of each component in the link as well as their capabilities when deployed in a system. To truly understand and optimize the channel, connector manufacturers are now taking into account a variety of factors, such as the impact of pc-board material, thickness, plated through-hole vias and transceiver devices, on the performance of their high-speed interconnect solutions. They are developing simulation and modeling tools that characterize the entire signal path from the semiconductor device to the backplane, and are teaming up with silicon vendors to accurately model the transceiver, connector and pc-board signaling performance.

During the past several years, electrical specs such as skew, attenuation, signal integrity and crosstalk have become critical design issues for connector manufacturers, but today silicon and mechanical attributes have become just as important.

The challenge is to understand the interaction of all of those components together and then make the right trade-offs to optimize the functionality, reliability and cost of the system, said Tom Pitten, development engineering manager for Teradyne Connection Systems (Nashua, N.H.).

Tyco Electronics (Harrisburg, Pa.) calls this new approach an "active interconnect" philosophy, because it takes into account how every component performs in the channel and looks at issues affecting the passive channel, such as the type of pc-board materials used and alternative drilling techniques.

"As the speeds have migrated upward, we have a lot of concerns," said John D'Ambrosia, manager of semiconductor relations at Tyco Electronics. "The techniques that chip vendors implement have a significant impact on connector issues, and it has become more critical to understand all of the implications of electrical performance as well as the mechanical design," he said.

Such a strategy has produced a number of partnerships between connector manufacturers and silicon vendors. It has also prompted some connector makers to involve themselves with standards bodies trying to develop standard test methodologies and interoperability solutions for high-speed backplanes. The goal is to ensure satisfactory system performance at data rates higher than 2.5 Gbits/s and 3.125 Gbits/s.

In order to appreciate these developments, it's necessary to understand two things. The first is that most of today's 10-Gbit/s implementations are based on four channels, or lanes, at 3.125 Gbits/s; the second is that interconnect requirements for 3.125 Gbits/s per channel vs. 10 Gbits/s per channel differ significantly. The true design challenge in the physical implementation sits squarely at 3.125 Gbits/s, Pitten said. Another hurdle exists, though: Connector manufacturers are just now beginning to provide their customers with the same test vehicles they use for validation, putting to good use what they learned from OEM complaints about the connector industry's ability to provide the proper test data when it first moved into the10-Gbit/s realm from 1 Gbit/s.

"Initially, we didn't understand what was required in the testing methodologies in terms of test boards, test fixtures and test vehicles," said Bob Thornton, director of marketing for Fujitsu Components America Inc. (Sunnyvale, Calif.). "It isn't just validating the test data, it's also ensuring that the electrical simulation models that you provide to the customer for their modeling have also been validated."

In addition to developing accurate test methodologies to demonstrate the capabilities of their high-speed interconnects at higher data rates, connector makers are also optimizing transmission links with an eye toward containing costs. A central question in the industry right now is how far the connector companies can push standard FR4 backplanes without having to move to higher-performance, more expensive materials.

To extend the life of FR4 boards and improve the electrical performance of copper backplanes, some connector companies are trying different design techniques in their interconnect products, such as adaptive equalization or pre-emphasis equalization in conjunction with new connector technology.

One of the more popular techniques touted during the past couple of years is counter-boring plated through-hole vias to reduce the capacitance effect of the vias and to improve system performance. While some connector manufacturers believe this to be a reliable technique, others, like Teradyne Inc. (Boston), are focused on improving the reliability, scalability and cost implications of the added manufacturing process in production.

In addition to traditional connector performance measurements such as reflections and crosstalk, performance criteria have also become important. The acceleration of bit error rates as a qualification for the transmission channel performance has emerged as a significant development of the past two years, as has the way connectors interface with the cable, pc-board and silicon interface, said Gus Panella, engineering manager for the systems development group at Molex Inc. (Lisle, Ill.).

Many of the major connector manufacturers are working with standards bodies to develop interoperability standards by addressing important issues associated with higher-speed backplanes. One of the newest guides to flow from this effort is the High-Speed Backplane Initiative (HSBI), which facilitates the development of serial-link technology capable of data rates between 4.976 Gbits/s and 6.375 Gbits/s in a backplane up to a distance of 30 inches. The companies involved represent the network equipment, system, optical, connector and semiconductor industry sectors.

The HSBI is trying to develop a standard solution for some type of interoperability, which is needed in the industry, said Bob Pokrzywa, vice president of global marketing for FCI (Etters, Pa.). "Our customers need a way to compare apples to apples when it comes to high-speed backplane connectors."

Even when looking at speeds of 2.5 and 3.125 Gbits/s, interconnect and semiconductor manufacturers learned a lot from each other, Pitten said. "The semiconductor companies can do a lot of things to improve the link performance by understanding what the problems are in the entire backplane link," he said.

In the meantime, connector manufacturers are working with silicon manufacturers and test equipment vendors to create evaluation or reference platform kits to help customers validate their high-speed interconnect solutions in their particular application. Those kits or platforms take into account a number of variables that include pc-board materials and thickness, trace lengths and connector and transceiver types.

For example, Teradyne's Connection Systems Division and Accelerant Networks Inc. now offer a 6.25-Gbit/s backplane reference platform that integrates Accelerant's AN5500 five-port, 6.25-Gbit/s backplane transceiver with Teradyne's VHDM-HSD connector over 32 inches of an FR4 backplane. The package includes schematics, layout, models and software tools to help in the designer's evaluation, optimization and characterization of backplane elements.

Teradyne, in conjunction with Cadence Design Systems Inc. and Xilinx Inc., also recently introduced an extended version of the Rocket I/O Design Kit for SPECCTRQuest, the Cadence signal-integrity analysis tool. The hardware design kit, consisting of an Xaui-compliant 10-Gbit/s backplane solution for field-programmable gate arrays and Teradyne's VHDM-HSD connectors, enables users to simulate and validate multigigabit-per-second, system-level interconnections to accurately model transceiver, pc-board and connector performance.

"We developed multiple types of test vehicles and reference designs for interconnect products in our backplane system because there are a lot of different variables, including connector, board materials and board thicknesses, that have a big impact on the overall system performance," Pitten said. "We have multiple test vehicles that we've developed to characterize the performance of the links passively and actively with semiconductor devices.

"We try to deliver a reference platform that gives our customers all the data they need for simulation and actual measurement, and physical hardware that they can test to help accelerate their product development cycle," Pitten continued. He noted that no industry standard exists that governs ways of characterizing links, but standard techniques, eye-pattern analysis among them, do exist to measure performance.

Similarly, Tyco has begun offering evaluation kits for both its HM-Zd and MultiGig product line, to enable customers to do their own system testing. The models take into account other effects of the system pc board, D'Ambrosia said. Both PICMG and VITA have adopted Tyco's Zd connectors for their new high-speed backplane architectures.

Earlier this year, Tyco Electronics, along with semiconductor partner Gennum, demonstrated the Z-Pack HM-Zd connector, printed-wiring board and Gennum's chip technology running at 10 Gbits/s serially over 22 inches of FR-4 with standard board processing technologies.

Tyco's Xaui HM-Zd platform won approval from the 10-Gigabit Ethernet Alliance Xaui Interoperability Group and 10-Gigabit Ethernet Consortium as the common platform for interoperability testing. This means a common environment now exists for performance comparisons between Xaui solutions from different vendors. The Xaui electrical interface consists of four differential channels or lanes operating at 3.125 Gbits/s each to provide an aggregate raw bandwidth of 12.5 or 10 Gbits/s of Ethernet data.

In addition to partnering with silicon manufacturers, connector makers are finding they must work with CAD-tool and test-equipment manufacturers to develop software and equipment needed to perform new test measurements.

The industry has used S-parameter measurements for several years for single-ended domains, but performing differential S-parameter measurements has exposed equipment limitations. According to Panella, the test-and-measurement equipment available in the market is suitable for single-ended measurements only. This means that Molex has to do a multitude of single-ended measurements and mathematically extract differential measurements, he said.

A better way is to develop a true test method, making true differential drivers and vector analyzers for differential measurements, Panella said.

Another challenge high-speed connector manufacturers must meet is to provide standard artwork to board manufacturers for counter-boring vias. No standard exists in the CAD tool set that generates the circuit-board design for spec-ing out and electronically transferring the instructions for counterboring these holes, said Teradyne's Pitten. "We have to work with CAD tool companies on design software for creating artwork sets in the fabrication data."

Company Contacts

FCI's Communications Data and Consumer Division
(800) 237-2374
www.fciconnect.com

Fujitsu Components America Inc.
(800) 380-0059
www.fcai.fujitsu.com

Molex Inc.
(630) 969-4550
www.molex.com

Teradyne Connection Systems
A division of Teradyne Inc.
(603) 879-3600
www.teradyne.com/tcs

Tyco Electronics
A unit of Tyco International Inc.
(800) 522-6752
www.tycoelectronics.com