Verification vendors @HDL, Avery Design Systems and Axis Systems all will endorse Sugar, which originated at IBM Corp. Esterel Technologies, 0-In Design Automation and TNI/Valiosys have also recently announced or confirmed plans to support Sugar. These vendors join several others that previously announced tool support, and still others who endorsed the language when Accellera selected it for standardization in April.

Sugar isn't yet a formal standard, however, causing some to delay implementation. And some vendors have expressed concern that they now have to support two assertion languages: Sugar and OpenVera.

"There are currently about 10 EDA tool providers who plan to support Sugar in their respective verification offerings, and the number is growing," said Yaron Wolfsthal, manager of formal methods at IBM's Haifa, Israel, research lab, which created Sugar. "Of particular significance, I believe, is that many of these companies are collaborating and sharing technical and marketing information about Sugar, to ensure interoperability of their tools."

Wolfsthal named Avery, Cadence Design Systems, Esterel, IBM, Nobug Consulting, TransEDA and 0-In as simulation providers with Sugar tools. He pointed to @HDL, Cadence, Esterel, IBM and TNI/Valiosys as formal-verification companies with Sugar tools, and Verplex as a formal vendor with Sugar support in the pipeline.

Meanwhile, the Sugar 2.0 language reference manual has gone to Accellera's formal-verification technical committee for approval, said Harry Foster, Verplex CTO and committee chair. "Our goal is to complete the review by early November. It would then be handed off to the Accellera board for approval late this year," he said.

This means, however, that the current Sugar 2.0 specification could change. Further, Accellera still needs to determine which elements of the OpenVera assertion language will be added to SystemVerilog 3.1, and how Sugar and OpenVera will be aligned once that happens. SystemVerilog 3.0 has an assert construct derived from the Superlog language.

Low-cost learning tool

Not only will @HDL announce Sugar support, but it will also roll out a new product, @Verifier 101. This low-cost, limited-capacity version of the company's @Verifier product provides a unified flow for assertion-based verification, including formal model checking, simulation and debugging.

Both @Verifier and @Designer, the company's graphical design and debugging tool, will support Sugar, said Richard Curtin, @HDL's chief operating officer. "We're probably looking toward the end of the year," he said. "The issue right now is the flux of the Sugar 2.0 standard." The company has already announced support for OpenVera assertions and is working with beta customers on that support. Curtin said that both Sugar and OpenVera assertions will be supported natively, with no translation needed. Eventually, he said, @HDL will phase out its proprietary assertion language, as a standard solidifies. But it's awkward, he acknowledged, to have to support two standards.

"In our flow there's no penalty for using either, so we can equally support both. But as the market matures, we expect to see some amount of final unification," Curtin said.

The @Verifier 101 tool, meanwhile, is a full-function version of @Verifier that will support both Sugar and OpenVera. It includes a self-study learning package for assertion-based verification, along with "quick-start" design examples. It will be available in October on Linux and Solaris platforms at $995 for a 30-day license and $1,495 for a 60-day license.

"It's set up like a tutorial training version," Curtin said. "We haven't set the hard limits on it yet, but it might be up around 5,000 or 10,000 gate equivalents."

Axis announced an Assertion Processor module for its acceleration and emulation products last month. This module supports 0-In assertions now, and also supports the Open Verification Library of Verilog assertions. Support for OpenVera assertions is planned for next year.

Axis will announce that its Assertion Processor will also support Sugar 2.0 assertions. But full support is not likely to occur until late 2003, said Steve Wang, Axis' vice president of marketing. "There's still some debate regarding the official constructs for Sugar," Wang noted.

The Assertion Processor, he said, will let users write Sugar assertions that are then compiled, not translated, into Axis' reconfigurable-computing engine. The process will be transparent to the user, he said. The Assertion Processor claims to run assertion checks at least 1,000 times faster than a software simulator. "If there was one standard, it would be great, but our system is open enough that we can support different kinds of assertions," Wang said.

Avery, for its part, will support Sugar 2.0 in its TestWizard 2.0 testbench development solution, slated for release early in the fourth quarter. TestWizard supports on-the-fly simulation of assertions, and it works with Cadence, Synopsys and Model Technology HDL simulators.

Vice president of marketing Chris Browy said Avery has developed a "converter" that translates Sugar properties into TestWizard's native assertions. Then, they can be included in VHDL or Verilog source code. "It's very efficient and high performance," he said. "TestWizard has assertion functions, and it's almost a one-to-one translation from Sugar to those."

Because Sugar is interoperable between formal model checkers and simulators, and serves both VHDL and Verilog, it's more robust than SystemVerilog assertions, Browy said. Still, he noted, "we had hoped there would be some convergence in these [Accellera] efforts before they were announced."

Late last month, 0-In announced a version of its CheckerWare library that supports Sugar. This library contains "assertion IP" (intellectual property) for on-chip interfaces and RTL structures, such as arbiters, state machines and FIFOs. Monitors in the library check protocol rules for standard buses, memory interfaces and communications protocols. "We've inserted Sugar primitives into the library, so tools that can read Verilog and Sugar can work off of that CheckerWare IP," said Emil Girczyc, 0-In's president and chief executive officer.

But monitors in this special CheckerWare version are written in Verilog as well as Sugar, he noted. "Some things are easier to describe in Verilog; other things are easier to describe in Sugar."

The Sugar support is going into beta testing now. If the standard changes, Girczyk said, it will be "a very simple process" to update the library. Girczyk also said his company is "watching" OpenVera.

TNI-Valiosys announced early this month that its improved HDL formal property checker now supports Sugar. The product can be used to formally check the functional behavior of bus interface controllers and can capture protocol temporal relationships in Sugar.

Esterel Technologies will support Sugar in an upcoming release of its Esterel Studio formal-verification product, said COO Jean-Marc Talbot. He said assertions described in Sugar will be automatically translated within Esterel Studio and accessible in graphical or textual mode.

Cadence said in May that its Verification Cockpit will support Sugar 2.0, and TransEDA tipped Sugar support for its VN-Property DX checker in June and also announced integration with Novas Software's Debussy debugging environment. That means Sugar properties verified in simulation can be debugged with Debussy. NoBug Consulting, a design services firm, offers a Sugar2e Translator that translates Sugar 1.0 properties into Verisity's "e" language. And IBM's Haifa research lab supports that language with its RuleBase formal-verification tool.

When Accellera first announced the Sugar standard in April, EDA vendors including Cadence, Co-Design Automation, Mentor Graphics, Novas, Real Intent, Trans-EDA, Veritable, Verplex, Structured Design Verification and 0-In all endorsed the new standard and stated their intent to support it. Some of these vendors, however, also support OpenVera assertions or have plans to do so.