Innovative Semiconductors Inc. (Sunnyvale, Calif.) and eSilicon Corp. (Sunnyvale) have announced that eSilicon has licensed Innovative's USB 2.0 mixed-signal transceiver core. According to the companies, eSilicon will integrate Innovative's SL200 USB 2.0 transceiver macrocell into eSilicon's design and manufacturing flow.

Innovative's mixed-signal blocks include USB, IEEE-1394 PHY, phase-locked loops, and clock and data recovery. Its library of analog macrocells includes DAC, voltage converters and bandgap reference voltage. Innovative said all of its cores have been verified in silicon. The SL200 has also been certified for USB 2.0 compliance.

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Amphion Semiconductor Inc. (Belfast, Northern Ireland) has added MPEG-4, MPEG-2 and JPEG2000 compression Advanced Microcontroller Bus Architecture (Amba) interfaces for ASIC- and FPGA-targeted versions of its hardware accelerator cores.

According to the company, the addition of compression to the Amba High-Performance Bus (AHB) makes the cores better-suited for Amba-based SoC designs, such as those leveraging RISC microprocessor cores from ARM and other processor intellectual-property (IP) providers.

The first Amphion accelerator cores to support on-chip bus interconnectivity in compliance with the Amba spec are the CS6701 MPEG-4 video encoder and the CS6551A MPEG-2 video decoder. The encoder is an optimized hybrid hardware-and-software solution for low-bit-rate MPEG-4 encode applications. The decoder is a single-stream MP@ML version of the company's multistream technology for MPEG-1- and -2-compliant compressed video.

Also ported for AHB is the Amphion CS6510 JPEG2000 encoder, a high-performance, 172k-gate implementation for JPEG2000-based real-time image-coding systems.

JPEG2000 is the new "wavelet transform"-based standard for digital-still-image compression. According to the company, JPEG2000 renders significantly crisper text and graphics than JPEG at compression ratios up to 40:1, compared with the 20:1 limit of JPEG.

The CS6510 core carries out such computationally intensive tasks as wavelet transform, entropy coding, quantization and data scheduling, freeing the on-chip embedded processor to control such tasks as user-interface management and data formatting. Amphion claims the core complies fully with the ISO/IEC 15444-1 standard and performs full-motion image encode at up to 60 Megasamples/second in 0.18-micron process technologies.

IP interface vendor TriCN Inc. (San Francisco) secured $4.5 million in an initial round led by Rocket Ventures and Trinity Ventures. Robert Winter, general partner and managing director of Rocket Ventures, and Fred Wang, general partner of Trinity Ventures, have each taken a seat on TriCN's board. The company (www.tricn.com) plans to use the funding to expand its portfolio of interface IP.