By using the same simulation-based design process as that used for the Stratix family, the company has developed an FPGA architecture that European marketing director Paul Hollingworth says works out at less than half the die size of the nearest competitor and 60% cheaper.

"Traditionally, FPGA vendors have taken the approach to low-cost products of taking stuff out," said Hollingworth. "We have designed Cyclone from the ground up based on customer requirements. It's not rocket science, but not something that's happened in the industry as a whole.

"We used the same modelling tool as that used on Stratix to check the proposed architecture against customer requirements."

Altera used software written by Toronto specialist Right Track CAD, a company that the FPGA maker bought to help bring its Quartus software back on track. Right Track had also written an FPGA simulation environment which Altera was able to put to use.

Although simulation confirmed that the base logic cell was on the right track, it identified that the original proposed architecture, derived from Stratix, was over-resourced on routing wires.

"That was a surprise from the simulation," said Hollingworth.

Cyclone is intended to scale up to about 35 000 logic elements while Stratix is designed to handle 200 000.

"It was easy to strip out some routing. Stratix, to an extent, was over-routed from an engineering perspective because you would always expects some designs to be pathological. Stratix can route pretty much anything we can have thrown at it," said Hollingworth.

"Where we can take cost down by 50¢, we would decide to take those extra metal layers out of Cyclone."

Built on the same TSMC 0.13µm copper process as that to be used for Stratix, the Cyclone parts use a simpler memory structure than the more expensive parts.

"It lies between the per-logic-element memory of Apex and what we have in Stratix. We have gone with a single-sized 4Kbit block that can run at 200MHz. We can split it into sub-blocks that can have different widths, such as 58 or 516."

The company has put 130 LVDS ports into the biggest device together with a double-data rate (DDR) SDRAM controller.

"DDR will become the standard and people won't pay extra for that," said Hollingworth.

The reason behind the large number of LVDS ports lies in the move by some high-end consumer products to favour differential signalling in their systems to improve noise immunity — although it is also partly because the relative small size of the cell makes it economically viable.

Configuration on the cheap

Altera has changed the way it handles logic configuration with the introduction of the Cyclone.

Previously, the configuration logic sat in a dedicated eprom chip, demanding that the company ships both the FPGA and its own range of memories. For this family, Altera has decided to put the configuration logic into the FPGA so that it can take the set-up data from a standard memory device.

Altera will supply its own configuration chips, sourced from a memory specialist, but it expects many volume projects to fold the FPGA data into the same device as that used for processor code storage.

"Most people will use a microcontroller and flash," said Paul Hollingworth, European marketing director.