Because of the high cost of customized design solutions, new design rules are needed from central R&D or a design group to efficiently include the protection solution as an integral part of the high-level design methodology.

With design-for-test (DFT), designers had to define the strategy early in the design definition phase. The addition of test circuitry infrastructure intellectual property to the functional IP guaranteed a high yield for high-volume production. So about 10 years ago, a new skill function was born: the DFT engineer. Now the whole semiconductor industry has accepted the necessity of paying for silicon area overhead that guarantees high-quality ICs.

Today designing circuits for high fault coverage using conventional DFT techniques is not enough. We also need to account for new SEU phenomena in all very deep-submicron devices to be able to guarantee high quality and decrease system failure-in-time (FIT) rate. Adding infrastructure IP for robustness is becoming mandatory. As a consequence, a new domain of competence will soon emerge: the fault-tolerant architect (FTA) engineer.

Early in the chip architecture definition phase, the FTA engineer will plan the necessary fault-tolerant infrastructure IP needed to achieve the FIT required by the customer or the company's quality policy. Each subpart of the circuit will be carefully analyzed with new dedicated simulation tools, and protection will be added just where needed, avoiding a pure triplication technique and thus reducing the area overhead.

New skills are required to develop a comprehensive soft-error correction plan, and different solutions should be used for different blocks and system components. Tools are arriving now to address these features.

The FTA engineer will possess some physics knowledge of cosmic rays and alpha-particle effects in order to understand the failure mechanisms generating the SEU data and choose the best design technique for robust implementation. The engineer will be able to set up a radiation test campaign to assess and verify device robustness.

Evidence shows that scientists understand only the tip of the iceberg in the range of particle effects on semiconductors. Care in designing test procedures is essential to achieve a meaningful soft error rate (SER). Only well trained engineers like FTAs can handle this in a design group. Obtaining valuable SERs and understanding their origin will help the design team pinpoint the problem areas and develop the best strategies at an early stage in the product design cycle.

The industry must adopt standards for testing methods and for SER. That will help to establish reasonable FIT rates for chips and systems-on-chip. Information sharing is important to fine-tune test procedures.

At iROC, for example, we are working with computer systems vendors and their commercial SRAM/DRAM suppliers to implement neutron-beam testing to obtain valid data leading to SER qualification.

Philippe Silvestre is director of engineering for iROC Technologies (Santa Clara, Calif.), a supplier of infrastructure ip to boost chips' robustness against faults.