The process isn't cheap: Eventually, it could cost about 50 percent more than a bonded-type SOI wafer, according to AmberWave CEO Mark Wolf. In strained-silicon on silicon-on-insulator (SS-SOI), the relaxed SiGe layer normally is left intact to provide a strain on the thin top layer of silicon.

Achieving strained silicon on an SOI wafer normally involves forming a thin (20- to 50-nanometer) combined layer of SiGe and strained silicon, a difficult thickness to achieve for the combined SiGe-Si films.

In the AmberWave process, presented at the recent IEEE SOI conference in Williamsburg, Va., strained silicon is flipped onto an oxide layer. A SiGe layer is created and planarized by chemical mechanical polishing to remove the crosshatch surface roughness. The CMP step is key to controlling the thickness of the top films, said AmberWave co-founder Mayank Bulsara, who worked on the process development.

A 200-nm SiGe layer is deposited on the planarized SiGe, and then a thin layer of strained silicon is created on top. Hydrogen is implanted through the strained-silicon layer to induce a cleave plane, allowing the wafer to be split later in the process.

Next, the implanted structure is bonded to an oxidized silicon handle wafer. The transferred silicon germanium layer is oxidized and etched away selectively, with the oxidation stopping at the layer of strained silicon. The result is a thin layer of strained silicon bonded to an oxide layer.

"Creating a silicon layer that is tens of nanometers thick normally is very difficult. By bonding an integrated strained-silicon layer on top of the oxide, there are no fundamental issues to keeping the silicon layer as thin as possible," said Bulsara.

Twin challenges

The process removes the twin challenges of SiGe thermal instability and contamination from the germanium atoms. And without the SiGe layer, the top active layer can be thinner, which is important to achieving a fully depleted state, Bulsara said.

CEO Wolf said the process could improve the device drive current significantly. But the process is in the developmental stage and will take several years to work out, Wolf added.

AmberWave is a spinout from the Massachusetts Institute of Technology, which offers a licensable form of strained-silicon technology. Advanced Micro Devices Inc. has confirmed that it is working with AmberWave on an SS-SOI process, and several other customers are using AmberWave's intellectual property for 130-nm strained-silicon devices fabricated at an unidentified foundry in Taiwan.